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EMI-immune analogue circuit generated through genetic evolution

EMI-immune analogue circuit generated through genetic evolution

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Specifications are getting higher while environmental circumstances become harsher. Electromagnetic immunity is one of the challenges that future IC designers have to face. A new methodology is presented that allows optimisation of analogue circuits towards their specification while simultaneously evolving them towards a high electromagnetic immunity. Results are illustrated on a current mirror structure, resulting in a new EMI-immune topology.

References

    1. 1)
      • IEC 62132-1, Ed. 1.0: ‘Direct RF power injection to measure the immunity against conducted RF-disturbances of integrated circuits up to 1 GHz’.
    2. 2)
    3. 3)
      • Richardson R.E. . Quiescent operating point shift in bipolar transistors with AC excitation. IEEE J. Solid-State Circuits , 1087 - 1094
    4. 4)
      • Casier, H.: `Trends in automotive electronics', Proc. 5th Int. Conf. on Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), 2004.
    5. 5)
      • McConaghy, T., Palmers, P., Gielen, G., Steyaert, M.: `Simultaneous multi-topology multi-objective sizing across thousands of analog circuit topologies', 44thACM/IEEE, Design Automation Conf. (DAC ‘07), June 2007, p. 944–947.
    6. 6)
      • Gielen, G., De Wit, P., Maricau, E., Loeckx, J., Martin-Martinez, J., Kaczer, B., Groeseneken, G., Rodriguez, R., Nafria, M.: `Emerging yield and reliability challenges in nanometer CMOS technologies', Design, Automation and Test in Europe (DATE'08), 2008, p. 1322.
    7. 7)
    8. 8)
      • Worm, S.B.: `Simulation of {RF} immunity property of analog circuits', Proc. 11th Int. Symp. on EMC, 1995, Zurich, Switzerland.
    9. 9)
      • Redouté, J.-M., Steyaert, M.: `An improved current mirror structure insensitive to conducted EMI', EMC Europe Workshop, 2005, Roma, Italy.
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