Design and simulation of nano-arbiters using quantum-dot cellular automata

https://doi.org/10.1016/j.micpro.2019.102926Get rights and content

Highlights

  • Implementation of Nano-Arbiter circuits using Quantum-dot Cellular Automata (QCA).

  • Optimization of the QCA circuits using genetic programming.

  • Applying a two dimensional clock distribution to the QCA arbiter circuits.

  • Comparison of the QCA arbiter’s circuits using performance measures such as power dissipation, occupied area, etc.

Abstract

Arbiters are the essential components of the Network-On-Chip (NOC) systems and are used to resolve the contention problem where multiple requests must be handled for shared resources. On the other hand, with the ever-increasing downsizing trend in the fabrication technology, Quantum-dot Cellular Automata (QCA) with its nano scales and very low power consumption is a promising candidate for implementing future NOCs. In the current work, we design and simulate nano-arbiters using QCA with the following contributions: i) The 2-bit Basic Round Robin Arbiter (RRA) and the 2-bit Ping Pong Arbiter (PPA) are designed and simulated; ii) A solution for an erroneous condition found in the original circuit of RRA is reported and fixed; iii) We use Cartesian Genetic Programming (CGP) approach to simplify the RRA and PPA designs; iv) In order to leverage our QCA designs, we apply a more realistic clock distribution (2-DW clocking) and report the results. At the end, a one-to-one comparison of the two arbiters designed with QCA will be presented using such benchmarks as area, latency, etc. Our results show that in the 2-bit input mode, the PPA arbiter has the best overall performance.

Introduction

With an ever increasing pace in the development of fast and compact chips in the semiconductor market, the number of integrated cores in a single chip has dramatically increased. This trend inevitably leads to new paradigms in the fabrication, interconnections, and integration processes. An example is the so called System on Chip (SOC) where the scales of a multi-component system is supposed to be miniaturized at chip scales. With this miniaturizing trend, naturally new challenges have raised up as the flexibility and the freedom in the arrangement and interconnections provided in large scales are swapped with various physical and technical restrictions. One such restriction arises in interconnecting core components in the SOC designs. This is not a trivial problem if one notices the multitude of bus lines between components in an otherwise tiny space.

In this regard, although many interconnection paradigms have been proposed, nonetheless each one comes with its own drawbacks. For instance, the traditional shared-bus paradigm suffers from several limitations including bandwidth, power consumption, and clock synchronization [1]. As a result, ideas from computer networking have been put forward as a solution for the drawbacks in the traditional interconnections strategies. This has led to the Network On Chip (NOC) [2], [3] design schema as promising candidates for handling the interconnection problem in SOCs [4]. NOC designs mainly consist of a network of routers (nodes) that are connected to each other by some communication links with the advantage of being more scalable and reliable.

In a NOC design, the router is the main building block [5], which is supposed to receive packets from the source, and then according to a routing strategy and network topology transmits packets to its immediately attached core or other routers [6], [7]. In addition, the routers determine the overall strategy for moving data throughout the whole NOC perimeter and performs the flow control policies (routing, arbitrating, etc.). One important constraint on the performance of a router is the handling of the contention between multiple agents (multiple requests) in accessing a shared resource. This is the place where arbitration logic and control functions are implemented in routers [2], [8]. Generally, an arbiter is the main element in shared resource systems such as routers that it is usually placed where the major bottleneck for the throughput exists. It must preserve a fair arbitration in response to the received requests [9] and consumes less power in a minimum area. Hence, the delay, the layout area, and the power consumption are the candidate benchmarks for the evaluation of arbiters.

In recent years, there has been a growing trend in the design and optimization of arbiters mostly based on the traditional transistor technology [10], [11], [12], [13], [14], [15], [16]. However, with the ever increasing downsizing trend in the fabrication technology, the frontier of this trend has now touched nano-scales. In those scales, the size, the power consumption, and the interconnection facilities are among the most intriguing challenges confronted by design strategies such that those paradigms (such as QCA) that offer a higher fabrication density, lesser power consumption, and more flexibility in interconnections down to atomic and molecular scales [17], [18].

Our aim in this work is to evaluate the potential of QCA in implementing NOC components. Specifically, due to the importance of the arbiter module, we present the results of the design and simulation of two arbiter architectures, namely, the 2-bit Basic Round Robin Arbiter (RRA) [2] and 2-bit Ping Pong Arbiter (PPA) [19]. While performing simulations on our QCA design we noticed a fault in one of the original designs, which is also reported and fixed. Further enhancements of the obtained QCA designs are provided through two steps. First, we apply a genetic programming approach (CGP) to simplify the bare QCA designs and reach at more efficient circuits in terms of the number of the components as well as their arrangements. Second, the operational differences of the QCA circuits under a more realistic clock distribution are analyzed and the results will be reported. We also report the QCA realization for the arbiter circuits and eventually compare them in terms of the layout area, crossover, clock cycles (latency), power dissipation, and a QCA-specific cost function representing the design complexity.

The paper is organized as follows. In Section 2, a brief introduction to QCA will be presented. Some recent related works on the arbiter architecture together with the utilization of QCA in the design of the interconnection strategies are explored in Sections 3 and 4. The QCA realization of arbiters, comparisons of results, and the 2-DW clocking scheme are respectively presented in Sections 5–7. Finally, some conclusive remarks are made in Section 8.

Section snippets

Quantum-Dot cellular automata (QCA)

QCA circuits are constructed from basic building blocks called QCA cells shown in Fig. 1a. Schematically, each cell consists of four quantum dots located at the corners of a square. Physically though, the cell could be any quantum system with four possible positions for two electrons. With this arrangement, two electrons (in fact the probability density of electrons) could probabilistically occupy any of those quantum dots. However, because of the repulsive Coulomb force between electrons,

Basics

The main task of an arbiter is the scheduling and prioritization between input requests for shared resources. Fig. 4 shows a schematic diagram of an arbiter consisting of two parts [23]. The first part is a programmable arbitration logic that decides which requests are granted according to the current state of the priority vector. The second part is the pointer update logic that decides which of the requests in the next cycle will be prioritized according to the current grant vector. Given the

Related works

With the ever increasing demand for the compact size SOCs, the fabrication technology has been shifted from micro-scales to nano-scales. Accordingly, much more works seem necessary for the evaluation of the competency of the emerging nano-scale ideas such as QCA in the SOC applications. In the application of NOCs for example, a few developments in using QCA circuitry have recently been reported. For instance, [31], [32], [33], [34], [35], [36], [37], [38], [39], [40] have reported the

QCA realization of arbiters

In this section, we present the QCA design of the 2-bit Basic RRA and 2-bit PPA arbiters. We use QCADesigner with the bistable simulation engine [41]. The simulation parameters are presented in Table 3.

General performance analysis

In Section 5, three types of arbiters were realized using QCA. In this section, we evaluate and compare those realizations using such parameters as the number of QCA cells, area, QCA clock cycles (latency), and a cost function that is an exponential function of the number of majority gates, inverter gates, crossovers, and the latency. Table 4 gives the numerical values of the first three parameters for the three circuits. The cost function will be discussed in the next section.

Based on these

The QCA realizations using the 2-DW clocking

In this section, we use a more realistic clock distribution scheme in [47], [48] to draw QCA layouts of the RRA, the priority circuit and the PPA. The two dimensional wave (2-DW) clocking scheme is based on the parallel execution and processing in clocking zones within a different timing framework. This scheme have been proposed to overcome the limitations such as placing long lines of cells among clocking zones which leads to the thermal fluctuation issue. Therefore, for a fixed Ek (kink

Conclusions

Network On Chip is a solution for various constrains encountered in miniaturized SOCs, especially in nano-scales. In this paper, we explored the potential of QCA as a nanoscale proposal for the realization of a few arbiter’s architectures as the main component of the routers in NOCs. We examined three arbiter’s architectures, namely, the basic RRA, the proposed RRA, and the PPA. Meanwhile, we also explored the potential of genetic programming (CGP) for the optimization of the circuits, the

Declaration of Competing Interest

We confirm that there are no conflicts of interest associated with this manuscript and there has been no significant financial support for this work that could have influenced its outcome.

Jalal Rostami Monfared received his BSc degree from K. N. Toosi University of Technology, Tehran, Iran, in 2004, and MSc degree from Razi University of Kermanshah, Kermanshah, Iran, in 2010 both in Electrical Engineering. His research interests are Networks-on-Chip, quantum computation, integrated circuits, and artificial intelligence.

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  • Jalal Rostami Monfared received his BSc degree from K. N. Toosi University of Technology, Tehran, Iran, in 2004, and MSc degree from Razi University of Kermanshah, Kermanshah, Iran, in 2010 both in Electrical Engineering. His research interests are Networks-on-Chip, quantum computation, integrated circuits, and artificial intelligence.

    Abdolmajid Mousavi received his MSc degree in electrical engineering from the university of Tehran, Iran, in 1997. From 1997 to 2003, he was a manager and a computer networking consultant in an IT company, a lecturer at the University of Lorestan, and a consultant for electrical engineering standards in the National Institute of Industrial Research and Standardization in Iran. He enrolled in the PhD program of the department of electrical and computer engineering at the University of Calgary, in 2003 and graduated in 2009. During 2007 to 2009, he was a research associate in Canada Energy Research Institute. Currently, he is an assistant professor at the University of Lorestan, Iran. His main research interests are quantum computation and application of artificial intelligence in engineering.

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