A benchmark suite for designing combinational logic circuits via metaheuristics

Highlights

• A benchmark suite composed by a heterogeneous set of problems is proposed.

• Metaheuristics can be analyzed when designing combinational logic circuits.

• Performance measurements and statistical values are defined to compare the methods.

• A case study shows the advantages of the proposed benchmark suite.

Abstract

The evolvable hardware literature reports several methods for the evolution of digital circuits. However, there is a large variability in the set of problems and the appropriate metrics used for the evaluation of the results. In this paper, we propose a set of representative problems to comparatively evaluate metaheuristics when designing Combinational Logic Circuits (CLCs). We also define a set of performance measurements and descriptive statistics to analyze the results found by the search techniques. As a case study, we compare Cartesian Genetic Programming variants applied to this domain. The results highlight the benefits of the proposed heterogeneous benchmark suite in the analysis of metaheuristics when designing CLCs.

Introduction

Manually designing an efficient digital electronic circuit is a task that requires time and Boolean algebra expertise [1]. To assist this work, some deterministic algorithms can be found in the literature for Boolean functions minimization, such as the Quine–McCluskey [2] method and Karnaugh Maps [3]. However, these methods are limited in practice to problems with a small number of inputs variables, as the two-level logic minimization is an NP-complete problem [4]. Thus, circuits with a large number of variables have to be minimized with potentially non-optimal heuristic methods such as ESPRESSO [5].

ESPRESSO is a logic minimization software that uses a heuristic to efficiently reduce the complexity of logic circuits in terms of the number of logic gates. Instead of expanding the logic function in minterms, ESPRESSO manipulates “cubes” representing the product terms. There is no guarantee in finding the optimum solution, but usually, a reasonable solution is obtained. Compared to other traditional techniques, ESPRESSO is more efficient, as it requires lower memory usage and processing time.

On the other hand, evolutionary computing techniques applied to the evolution of digital circuits (Evolvable Hardware) have proved to be a competitive field, being able to find original designs and simplifications through association rules that are not commonly used by humans designers. However, this approach still faces scalability problems as the computational cost (notably the processing time) of the metaheuristics is strongly affected by the number of rows in the truth table, and this number grows exponentially with the number of inputs of the circuit.

Preliminary studies demonstrated that evolutionary computation techniques produce competitive results when compared to those created by using traditional methods, such as Karnaugh Maps and the Quine–McCluskey algorithm [6], [7], [8], [9]. However, these works only used digital circuits with a small number of variables (2–4 inputs and 1–3 outputs). Vasicek and Sekanina [10] were the first to evolve more complex benchmark circuits (8–41 inputs and 1–63 outputs), resulting in solutions with fewer logic gates when compared to common optimization methods. Still, there is a gap between the circuits from the literature and the real needs of the industry when it comes to the size of the circuits, mainly in terms of the number of inputs [11]. Hence, new algorithms are being developed to address known issues and improve existing methods [1], [12], [13].

The way that evolutionary computation techniques are analyzed in the literature is not uniform when it comes to the design and optimization of digital circuits. In each paper, the methods are compared to a particular set of problems, employing different objective functions and performance measurements. Only circuits with a small number of logic gates (3–4 inputs and 1–3 outputs) were designed in [14], where the optimization is broken in two steps: first, the absolute difference between the actual and the required output is minimized for finding a feasible solution; then, in the second step, the number of logic gates is minimized. Circuits with 3–16 inputs and 1–128 outputs were created in [15], and the techniques are evaluated regarding the number of generations required to find a feasible solution, the fitness function value, and the time required to solve the problem. The computational effort, the processing time, and the success rate when looking for feasible solutions were used in [10] to analyze the performance of the methods when applied to circuits with 8–41 inputs and 1–63 outputs. Circuits with up to 16 inputs and outputs were considered in [16], where the techniques were comparatively assessed concerning the number of objective function evaluations required to find a feasible solution and the success rate. Thus, it is possible to observe that there is no consensus on the set of problems for testing the techniques and the most appropriate metrics to measure the quality of these solutions. Also, the sets of logic gates supported by the search techniques are not the same among these works.

Due to these differences, the growing number of new proposals, and the widespread usage of evolutionary techniques for solving this type of problem, it is important to create and implement a new benchmark for the design of digital circuits. Thus, we propose here a benchmark suite to analyze and compare metaheuristics approaches for designing Combinational Logic Circuits (CLCs). This suite includes a set of digital logic circuits and the methodology for performance evaluation. The selected test-problems include circuits with different features (number of inputs, number of outputs, output balancing, and simplification ratio), covering a wide range of hardness degrees. The proposed methodology aims at helping the experimentation and the comparison among different methods for the evolutionary design of combinational logic circuits. Finally, we used Cartesian Genetic Programming (CGP) variants to illustrate the performance analysis of the results, as CGP is pointed out as the most efficient metaheuristic for the design and optimization of CLCs [17].

The remainder of this paper is organized as follows: Section 2 presents a review of the Evolvable Hardware literature, covering the techniques commonly used for the evolution of digital circuits. Section 3 introduces the CLC optimization problem addressed in this work. Section 4 presents the proposed benchmark suite, the selected test-problems, and the recommended performance evaluation methodology. Section 5 examines the Cartesian Genetic Programming and its methods for evolving digital circuits (this is the metaheuristic used in this paper for the computational experiments). Section 6 shows a case study using the proposed benchmark. Finally, Section 7 closes this paper with conclusions and future work.