Abstract
Evolutionary algorithms are an alternative option to the Boolean synthesis due to that they allow one to create hardware structures that would not be able to be obtained with other techniques. This paper shows a parallel genetic programming (PGP) Boolean synthesis implementation based on a cluster of FPGAs that takes full advantage of parallel programming and hardware/software co-design techniques. The performance of our cluster of FPGAs implementation has been compared with an HPC implementation. The experimental results have shown an excellent behavior in terms of speed up (up to ×500) and in terms of solving the scalability problems of this algorithms present in previous works.
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Pedraza, C., Castillo, J., Martínez, J.I. et al. Genetic Algorithm for Boolean minimization in an FPGA cluster. J Supercomput 58, 244–252 (2011). https://doi.org/10.1007/s11227-010-0401-7
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DOI: https://doi.org/10.1007/s11227-010-0401-7