Elsevier

Applied Soft Computing

Volume 9, Issue 2, March 2009, Pages 618-624
Applied Soft Computing

Practical and scalable evolution of digital circuits

https://doi.org/10.1016/j.asoc.2008.08.004Get rights and content

Abstract

This paper addresses the scalability problem prevalent in the evolutionary design of digital circuits and shows that Evolvable Hardware (EHW) can indeed be considered as a viable alternative design methodology for large and complex circuits. Despite the effort by the EHW community to overcome the scalability problems using both direct mapped techniques and developmental approaches, so far only small circuits have been evolved. This paper shows that, by partitioning a digital circuit and making use of a modular developmental approach, namely, the Modular Developmental Cartesian Genetic Programming (MDCGP) technique, it is indeed possible to evolve large circuits. As a proof of concept, a 5 × 5 multiplier is evolved for partition sizes of 32 and 64. It is shown that compared to the direct evolution technique, the MDCGP technique provides five times reduction in terms of evolution times, 6–56% reduction in area and improved fault tolerance. The technique is readily scalable and can be applied to even larger partition sizes, and also to sequential circuits, thus providing a promising path to evolve large and complex circuits.

Introduction

Recently, the idea of evolving hardware has attracted an increasing group of researchers [1]. Evolvable Hardware (EHW) uses reconfigurable logic devices like Field Programmable Transistor Arrays (FPTAs) and Field Programmable Gate Arrays (FPGAs) whose architecture can be reconfigured by evolutionary techniques. If new hardware functions are required, EHW can alter its own hardware structure rapidly and accommodate such changes in real time. The possibilities for such automatic design of electronic circuits using evolutionary algorithms have been explored both in the analog [2] and digital [3], [4], [5] domains. It has been found that evolutionary algorithms can in practice produce designs that are both efficient and beyond the scope of conventional methods [6]. Sekanina [7] has pointed out in his survey paper that innovative solutions can be produced irrespective of the evolutionary technique adopted. However, the size of the circuits evolved so far has been very small. This is because of the fact that most of these approaches look at the direct evolution technique, where the chromosome string length depends on the number of nodes (gates) used for evolution. As the complexity of the circuit increases, so does the chromosome length and there is an enormous increase in the design space. Such huge design spaces are very difficult to explore, even with evolutionary techniques. Another major concern is the time required to calculate the fitness value of the circuit. This increases as the number of input/output combinations increase. These problems are referred to as scalability problems and have limited the evolvability of practical circuits [8].

These scalability problems have been handled to some extent by introducing variable length chromosomes [9], function level evolution techniques [10], automatically defined functions [11] and increased complexity evolution [12]. Nevertheless, with direct evolution, the scalability problem still persists and limits the practicality of evolution.

This has motivated a number of researchers to explore the effect of biological development based modelling of the genotype–phenotype mapping, called the developmental approach, on scalability [13], [14]. There are instances in literature that demonstrate the fact that development can enhance scalability for pattern recognition problems [15]. Gordon and Bentley [16] have shown that development brings scalability to hardware evolution and have demonstrated it for 2-bit adder circuits. Miller and Thomson [17] have demonstrated the developmental principle using the Developmental Cartesian Genetic Programming (DCGP) technique and have constructed simple circuits like even parity and a 1-bit adder circuit. However, the development of other types of circuits has been reported to be difficult. Thus, the application of evolutionary techniques to evolve/develop large circuits is still far from reality. Our work addresses this scalability problem by extending the DCGP technique and proves that it is possible to evolve much larger circuits than those evolved so far.

We have shown earlier that the concepts of divide and conquer and reuse can be used to increase the scope of the DCGP technique. The concept of divide and conquer is adopted by dividing the circuit to be developed into partitions based on the input and output vectors, and developing the partitions separately [18]. Also, the partitioning process when examined reveals the fact that the output combinations of many of the partitions repeat. Therefore, such combinations are “reused” leading to a reduction in the evolution time [19]. However, even with partitioning and reuse of the repeating output combinations, it is found that the scalability problem still persists for large partition sizes.

Therefore, the present work proposes the Modular DCGP (MDCGP) technique and provides an integrated approach to evolve large circuits. This technique uses the circuits developed for smaller partition sizes as inputs to develop circuits for larger partition sizes. This effectively reuses the already developed smaller modules. The genotype and the phenotype nodes are suitably modified to handle this change. The technique is highly scalable and partition sizes of 32 and 64 are developed easily. To our knowledge, the 64-bit partitions are also the largest partitions evolved so far [12].

Moreover, as the evolved circuits are to be implemented on Field Programmable Gate Arrays, we also examine the practicality of evolution of the DCGP technique with respect to different types of FPGA structures, viz. coarse grain (using Configurable Logic Blocks (CLBs)) and fine grain (using gates) [20]. In addition to this, we compare the MDCGP technique with direct evolution and show that the MDCGP technique provides better evolvability, reduced area overhead and improved fault tolerance.

Thus, this paper addresses the scalability problem and shows that it is possible to evolve circuits larger than those reported so far through the following contributions:

  • Increase in the scope of the DCGP technique with the help of decomposition and reuse.

  • Introduction of the MDCGP technique.

  • Analysis of the practicality issues like evolvability, evolution time, area overhead and fault tolerance of the proposed MDCGP technique.

  • Comparison of the MDCGP technique with direct evolution, proving that the MDCGP technique has five times reduction in evolution time, 6–56% reduction in area and improved fault tolerance.

  • Proposal of a systematic procedure to evolve large digital circuits based on the analysis done.

The paper is organized as follows. Section 2 discusses the background and the motivation for this work. Section 3 proposes the MDCGP approach and gives details of the different techniques used for developing partitioned digital circuits. Section 4 provides the simulation results and discusses them. Section 5 concludes the paper.

Section snippets

Background and motivation

Several researchers have attempted to adapt the developmental approach for circuit design [13], [21]. The developmental approach is based on the natural evolution from cells to organisms. Miller and Thomson have proposed the DCGP mechanism that is based on the Cartesian Genetic Programming model [22] for the automatic evolution of digital circuits [17]. In the DCGP technique, a complex mapping is provided between the genotype and the phenotype. The idea here is to define a program, encoded as a

The proposed MDCGP technique

The DCGP technique uses two input gates in the phenotype structure. Instead, in order to increase the evolvability of the DCGP technique, the proposed MDCGP technique uses two input gates as well as three input, four input, or even larger input modules. When the circuit for a partition size of 8 is evolved, we obtain a 3-input module. For 16-bit partitions, it is a 4-input module and so on. The three input modules obtained with a partition size of 8 are used to evolve 16-bit partitions, that

Simulation results and discussion

A 5 × 5 multiplier has been considered for the study. However, it is to be noted that the concepts can be applied to a partitioned digital circuit of any arbitrary size. The 5 × 5 multiplier has been chosen as a proof of concept, and, because of the fact that this is the largest multiplier circuit evolved using direct mapping [12].

Three different techniques have been considered – two input gate based partitioned DCGP technique, unguided MDCGP (without freezing partial solutions) and guided MDCGP.

Conclusion

This paper has addressed the scalability problem prevalent in the evolutionary design of digital circuits by extending the DCGP technique with partitioning and reuse. The proposed MDCGP technique has been analysed with respect to evolvability, evolution time, area overhead and fault tolerance. A comparison with a partitioned direct mapped evolution technique has shown that MDCGP has reduced evolution times, area overhead and better fault tolerance. As the ultimate goal of this work is to show

References (30)

  • X. Yao, T. Higuchi, Promises and challenges of evolvable hardware, in: Proceedings of the International Conference on...
  • D. Keymeulen, A. Stoica, R.S. Zebulum, Fault-tolerant evolvable hardware using field programmable transistor arrays,...
  • M. Murakawa et al.

    Hardware evolution at functional level

  • J.F. Miller

    Digital filter design at gate-level using evolutionary algorithms

  • V.K. Vassilev et al.

    Towards the automatic design of more efficient digital circuits

  • J.F. Miller, D. Job, V.K. Vassilev, Principles in the evolutionary design of digital circuits—Part I, J. Genet. Prog....
  • L. Sekanina, Evolutionary design of digital circuits: where are current limits? in: Proceedings of the 1st. NASA/ESA...
  • V.K. Vassilev et al.

    Scalability problems of digital circuit evolution

  • M. Iwata, I. Kajitani, H. Yamada, H. Iba, T. Higuchi, A pattern recognition system using evolvable hardware, in:...
  • T. Kalganova, An extrinsic function-level evolvable hardware approach, in: Proceedings of the 3rd European Conference...
  • J.R. Koza

    Genetic Programming II: Automatic Discovery of Reusable Programs

    (1994)
  • J. Torresen, Evolving multiplier circuits by training set and training vector partitioning, in: Proceedings of the 5th...
  • P.C. Haddow, G. Tufte, P. van Remortel, Shrinking the genotype: L-systems for evolvable hardware, in: Proceedings of...
  • P. Eggenberger

    Evolving morphologies of simulated 3d organisms based on differential gene expression

  • P. Bentley et al.

    Three ways to grow designs: a comparison of embryogenies for an evolutionary design problem

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