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Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware

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Abstract

We propose to utilize a formal verification algorithm to reduce the fitness evaluation time for evolutionary post-synthesis optimization in evolvable hardware. The proposed method assumes that a fully functional digital circuit is available. A post-synthesis optimization is then conducted using Cartesian Genetic Programming (CGP) which utilizes a satisfiability problem solver to decide whether a candidate solution is functionally correct or not. It is demonstrated that the method can optimize digital circuits of tens of inputs and thousands of gates. Furthermore, the number of gates was reduced for the LGSynth93 benchmark circuits by 37.8% on average with respect to results of the conventional SIS tool.

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References

  1. F.V. Andrade, M.C.M. Oliveira, A.O. Fernandes, C.J.N. Coelho, Sat-based equivalence checking based on circuit partitioning and special approaches for conflict clause reuse, in IEEE Design and Diagnostics of Electronic Circuits and Systems (IEEE Comp. Society, 2007), pp. 1–6

  2. F.V. Andrade, L.M. Silva, A.O. Fernandes, in 26th International Conference on Computer Design, ICCD 2008. Improving SAT-based combinational equivalence checking through circuit preprocessing, 40–45 (2008)

  3. Berkley Logic Synthesis and Verification Group: ABC: A System for Sequential Synthesis and verification. http://www.eecs.berkeley.edu/~alanmi/abc/

  4. R.K. Brayton, G.D. Hachtel, C.T. McMullen, A.L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis. (Kluwer, Boston, MA, USA, 1984)

    MATH  Google Scholar 

  5. J. Cong, K. Minkovich, Optimality study of logic synthesis for LUT-based FPGAs. IEEE Trans. Comput. Aided Des. Integ. Circuits Syst. 26(2), 230–239 (2007)

    Article  Google Scholar 

  6. S. Disch, C. Schollm, in Asia and South Pacific Design Automation Conference. Combinational equivalence checking using incremental SAT solving, output ordering, and resets (2007), pp. 938–943

  7. R. Ebendt, G. Fey, R. Drechsler, Advanced BDD Optimization. (Springer, Berlin, 2000)

    Google Scholar 

  8. N. Een, A. Mishchenko, N. Sorensson, Applying logic synthesis for speeding up SAT, in Theory and Applications of Satisfiability Testing, LNCS, vol. 4501 (Springer, Berlin, 2007), pp. 272–286

  9. N. Een, N. Sorensson, MiniSAT. http://minisat.se

  10. P. Fiser, J. Schmidt, in Proceedings of 8th International Workshop on Boolean Problems. Small but nasty logic synthesis examples (2008), pp. 183–190

  11. H. de Garis, in International Conference on Artificial Neural Networks and Genetic Algorithms ICANNGA’93. Evolvable Hardware—Genetic Programming of a Darwin Machine. Innsbruck, Austria (1993)

  12. K. Glette, J. Torresen, M. Yasunaga, in Applications of Evolutinary Computing, EvoWorkshops 2007, LNCS, vol. 4448. An Online EHW Pattern Recognition System Applied to Face Image Recognition (Springer, 2007), pp. 271–280

  13. E. Goldberg, M. Prasad, R. Brayton, in DATE ’01: Proceedings of the Conference on Design, Automation and Test in Europe. Using SAT for combinational equivalence checking (IEEE Press, Piscataway, NJ, USA, 2001), pp. 114–121

  14. T.G.H. Gordon, P.J. Bentley, in Handbook of Nature-Inspired and Innovative Computing, ed. by A.Y. Zomaya. Evolving hardware (Springer, UK, 2006), pp. 387–432

  15. T.G.W. Gordon, P.J. Bentley, in Proceedings of the 2002 NASA/DoD Conference on Evolvable Hardware. Towards development in evolvable hardware (IEEE Computer Society Press, Washington, DC, US 2002), pp. 241–250

  16. G. Greenwood, A.M. Tyrrell, Introduction to Evolvable Hardware. (IEEE Press, New York, 2007)

    Google Scholar 

  17. P.C. Haddow, G. Tufte, P. van Remortel, in Proceedings of the 4th International Conference on Evolvable Systems: From Biology to Hardware, LNCS, vol. 2210. Shrinking the genotype: L-systems for EHW? (Springer, Berlin, 2001), pp. 128–139

  18. S. Harding, J.F. Miller, W. Banzhaf, in 2009 IEEE Congress on Evolutionary Computation. Self Modifying Cartesian Genetic Programming: Parity (IEEE Press, New York, 2009), pp. 285–292

  19. T. Higuchi, M. Iwata, D. Keymeulen, H. Sakanashi, M. Murakawa, I. Kajitani, E. Takahashi, K. Toda, M. Salami, N. Kajihara, N. Otsu, Real-world applications of analog and digital evolvable hardware. IEEE Trans. Evol. Comput. 3(3), 220–235 (1999)

    Article  Google Scholar 

  20. T. Higuchi, Y. Liu, X. Yao, Evolvable Hardware. (Springer, Berlin, 2006)

    Book  MATH  Google Scholar 

  21. T. Higuchi, T. Niwa, T. Tanaka, H. Iba, H. de Garis, T. Furuya, in Proceedings of the 2nd International Conference on Simulated Adaptive Behaviour. Evolving Hardware with Genetic Learning: A First Step Towards Building a Darwin Machine (MIT Press, 1993), pp. 417–424

  22. G. Hornby, A. Globus, D. Linden, J. Lohn, in Proc. 2006 AIAA Space Conference. Automated Antenna Design with Evolutionary Algorithms (AIAA, San Jose, CA, 2006), p. 8

  23. K. Imamura, J.A. Foster, A.W. Krings, in Proceedings of the 2nd NASA/DoD Workshop on Evolvable Hardware. The Test Vector Problem and Limitations to Evolving Digital Circuits (IEEE Computer Society Press, 2000), pp. 75–79

  24. T. Kalganova, J.F. Miller, in The First NASA/DoD Workshop on Evolvable Hardware. Evolving More Efficient Digital Circuits by Allowing Circuit Layout Evolution and Multi-Objective Fitness (IEEE Computer Society, Pasadena, California, 1999), pp. 54–63

  25. H. Katebi, I.L. Markov, in Design, Automation and Test in Europe, DATE 2010. Large-Scale Boolean Matching (IEEE, 2010), pp. 771–776

  26. P. Kaufmann, M. Platzner, Proceedings of Genetic and Evolutionary Computation Conference, GECCO 2008. Advanced Techniques for the Creation and Propagation of Modules in Cartesian Genetic Programming (ACM, 2008), pp. 1219–1226

  27. D. Keymeulen, M. Durantez, K. Konaka, Y. Kuniyoshi, T. Higuchi, in Proceedings of the 1st International Conference on Evolvable Systems: From Biology to Hardware ICES’96, LNCS, vol. 1259, eds. by T. Higuchi, M. Iwata, W. Liu. An Evolutionary Robot Navigation System Using a Gate-Level Evolvable Hardware (Springer, Tsukuba, Japan, 1997), pp. 195–209

  28. J.R. Koza, Genetic Programming II: Automatic Discovery of Reusable Programs. (MIT Press, Cambridge, MA, 1994)

    MATH  Google Scholar 

  29. J.R. Koza, F.H. Bennett, D. Andre, M.A. Keane, Genetic Programming III: Darwinian Invention and Problem Solving. (Morgan Kaufmann Publishers, San Francisco, CA, 1999)

    MATH  Google Scholar 

  30. J.R. Koza, M.A. Keane, M.J. Streeter, W. Mydlowec, J. Yu, G. Lanza, Genetic Programming IV: Routine Human-Competitive Machine Intelligence. (Kluwer, Dordrecht, 2003)

    MATH  Google Scholar 

  31. D. Mange, M. Sipper, A. Stauffer, G. Tempesti, Towards robust integrated circuits: the embryonics approach. Proc. IEEE 88(4), 516–541 (2000)

    Article  Google Scholar 

  32. J.F. Miller, D. Job, V.K. Vassilev, Principles in the evolutionary design of digital circuits—part I. Genetic Programm. Evol. Mach. 1(1), 8–35 (2000)

    Google Scholar 

  33. J.F. Miller, S.L. Smith, Redundancy and computational efficiency in cartesian genetic programming. IEEE Trans. Evol. Comput. 10(2), 167–174 (2006)

    Article  Google Scholar 

  34. J.F. Miller, P. Thomson, in Proceedings of the 3rd European Conference on Genetic Programming EuroGP2000, LNCS, vol. 1802. Cartesian Genetic Programming (Springer, 2000), pp. 121–132

  35. M. Murakawa, S. Yoshizawa, I. Kajitani, T. Furuya, M. Iwata, T. Higuchi, in Parallel Problem Solving from Nature—PPSN IV, LNCS, vol. 1141. Evolvable Hardware at Function Level (Springer, 1996), pp. 62–71

  36. T. Pecenka, L. Sekanina, Z. Kotasek, Evolution of synthetic RTL benchmark circuits with predefined testability. ACM Trans. Des. Autom. Electron. Syst. 13(3), 1–21 (2008)

    Article  Google Scholar 

  37. R. Poli, J. Page, Solving high-order boolean parity problems with smooth uniform crossover, sub-machine code gp and demes. Genetic Programm. Evol. Mach. 1(1–2), 37–56 (2000)

    Article  MATH  Google Scholar 

  38. L. Sekanina, in Applications of Evolutionary Computing—Proceedings of the 4th Workshop on Evolutionary Computation in Image Analysis and Signal Processing EvoIASP’02, LNCS, vol. 2279. Image Filter Design with Evolvable Hardware (Springer Verlag, Kinsale, Ireland, 2002), pp. 255–266

  39. L. Sekanina, Evolvable Components: From Theory to Hardware Implementations. (Natural Computing Series, Springer, Berlin, 2004)

    MATH  Google Scholar 

  40. E.M. Sentovich, K.J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P.R. Stephan, R.K. Brayton, A. Sangiovanni-vincentelli, Sis: A system for sequential circuit synthesis. Technical report, University California, Berkeley (1992)

  41. A.P. Shanthi, R. Parthasarathi, Practical and scalable evolution of digital circuits. Appl. Soft Comput. 9(2), 618–624 (2009)

    Article  Google Scholar 

  42. K.O. Stanley, R. Miikkulainen, A taxonomy for artificial embryogeny. Artif. Life 9, 93–130 (2003)

    Article  Google Scholar 

  43. E. Stomeo, T. Kalganova, C. Lambert, Generalized disjunction decomposition for evolvable hardware. IEEE Trans. Syst. Man Cybernet. Part B 36(5), 1024–1043 (2006)

    Article  Google Scholar 

  44. J. Torresen, in Proceedings of the 2nd International Conference on Evolvable Systems: From Biology to Hardware ICES’98, LNCS, vol. 1478, eds. by M. Sipper, D. Mange, A. Perez-Uribe. A Divide-and-Conquer Approach to Evolvable Hardware (Springer, Lausanne, Switzerland, 1998), pp. 57–65

  45. J. Torresen, A scalable approach to evolvable hardware. Genetic Programm. Evol. Mach. 3(3), 259–282 (2002)

    Article  MATH  Google Scholar 

  46. G.S. Tseitin, in Studies in Constructive Mathematics and Mathematical Logic, Part II. On the Complexity of Derivation in Propositional Calculus (1968), pp. 115–125

  47. G. Tufte, P.C. Haddow, Towards development on a silicon-based cellular computing machine. Nat. Comput. 4(4), 387–416 (2005)

    Article  MATH  MathSciNet  Google Scholar 

  48. Z. Vasicek, M. Zadnik, L. Sekanina, J. Tobola, in Proceedings of the 8th Conference on Evolvable Systems: From Biology to Hardware, LNCS, vol. 5216. On Evolutionary Synthesis of Linear Transforms in FPGA (Springer, Berlin, 2008), pp. 141–152

  49. V. Vassilev, D. Job, J.F. Miller, in Proceedings of the 2nd NASA/DoD Workshop on Evolvable Hardware, eds. by J. Lohn, A. Stoica, D. Keymeulen, S. Colombano. Towards the Automatic Design of More Efficient Digital Circuits (IEEE Computer Society, Los Alamitos, CA, USA, 2000), pp. 151–160

  50. M.N. Velev, Efficient translation of boolean formulas to CNF in formal verification of microprocessors, in Asia South Pacific Design Automation Conference (IEEE Computer Society, 2004), pp. 310–315

  51. J.A. Walker, J.F. Miller, The automatic acquisition, evolution and re-use of modules in cartesian genetic programming. IEEE Trans. Evol. Comput. 12(4), 397–417 (2008)

    Article  Google Scholar 

  52. S. Yanushkevich, D.M. Miller, V.P. Shmerko, R.S. Stankovic, Decision Diagram Techniques for Micro- and Nanoelectronic Design Handbook. (CRC, Boca Raton, 2006)

    Google Scholar 

  53. X. Yao, T. Higuchi, Promises and challenges of evolvable hardware. IEEE Trans. Syst. Man Cybernet. Part C 29(1), 87–97 (1999)

    Article  Google Scholar 

  54. R. Zebulum, M. Pacheco, M. Vellasco, Evolutionary Electronics—Automatic Design of Electronic Circuits and Systems by Genetic Algorithms. (The CRC Press International Series on Computational Intelligence, Boca Raton, 2002)

    Google Scholar 

  55. S. Zhan, J.F. Miller, A.M. Tyrrell, in Proc. of the 8th Int. Conference on Evolvable Systems: From Biology to Hardware, LNCS,, vol. 5216. A Developmental Gene Regulation Network for Constructing Electronic Circuits (Springer, Berlin, 2008), pp. 177–188

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Acknowledgments

This work was partially supported by the Czech Science Foundation under projects Natural Computing on Unconventional Platforms P103/10/1517 and Mathematical and Engineering Approaches to Developing Reliable and Secure Concurrent and Distributed Computer Systems GD102/09/H042 and by the research programme Security-Oriented Research in Information Technology MSM 0021630528.

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  1. Faculty of Information Technology, Brno University of Technology, Brno, Czech Republic

    Zdenek Vasicek & Lukas Sekanina

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  1. Zdenek Vasicek
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Correspondence to Lukas Sekanina.

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Vasicek, Z., Sekanina, L. Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genet Program Evolvable Mach 12, 305–327 (2011). https://doi.org/10.1007/s10710-011-9132-7

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