Skip to main content
Log in

Evolutionary design of complex approximate combinational circuits

  • Published:
Genetic Programming and Evolvable Machines Aims and scope Submit manuscript

Abstract

Functional approximation is one of the methods allowing designers to approximate circuits at the level of logic behavior. By introducing a suitable functional approximation, power consumption, area or delay of a circuit can be reduced if some errors are acceptable in a particular application. As the error quantification is usually based on an arithmetic error metric in existing approximation methods, these methods are primarily suitable for the approximation of arithmetic and signal processing circuits. This paper deals with the approximation of general logic (such as pattern matching circuits and complex encoders) in which no additional information is usually available to establish a suitable error metric and hence the error of approximation is expressed in terms of Hamming distance between the output values produced by a candidate approximate circuit and the accurate circuit. We propose a circuit approximation method based on Cartesian genetic programming in which gate-level circuits are internally represented using directed acyclic graphs. In order to eliminate the well-known scalability problems of evolutionary circuit design, the error of approximation is determined by binary decision diagrams. The method is analyzed in terms of computational time and quality of approximation. It is able to deliver detailed Pareto fronts showing various compromises between the area, delay and error. Results are presented for 16 circuits (with 27–50 inputs) that are too complex to be approximated by means of existing evolutionary circuit design methods.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7

Similar content being viewed by others

References

  1. R.E. Bryant, On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication. IEEE Trans. Comput. 40(2), 205–213 (1991)

    Article  MathSciNet  MATH  Google Scholar 

  2. R. Drechsler, B. Becker, N. Göckel, Genetic algorithm for variable ordering of obdds. IEE Proc. Comput. Digit. Tech. 143(6), 364–368 (1996)

    Article  Google Scholar 

  3. R. Drechsler, N. Göckel, B. Becker, in Learning Heuristics for OBDD Minimization by Evolutionary Algorithms. Parallel Problem Solving from Nature—PPSN IV. Lecture Notes in Computer Science, vol. 1141 (Springer, Berlin, 1996), pp. 730–739

  4. M. Duranton, K. DeBosschere, A. Cohen, J. Maebe, H. Munk, in Hipeac Vision 2015. Technical report (HiPEAC Network of Excellence, 2015). https://www.hipeac.net/publications/vision/

  5. R. Ebendt, G. Fey, R. Drechsler, Advanced BDD Optimization (Springer, Berlin, 2000)

    Google Scholar 

  6. H. Esmaeilzadeh, A. Sampson, L. Ceze, D. Burger, Neural acceleration for general-purpose approximate programs. Commun. ACM 58(1), 105–115 (2015)

    Article  Google Scholar 

  7. P. Fiser, Collection of Digital Design Benchmarks (Czech Technical University in Prague, Prague). http://ddd.fit.cvut.cz/prj/Benchmarks

  8. B.W. Goldman, W.F. Punch, Analysis of cartesian genetic programming’s evolutionary mechanisms. IEEE Trans. Evol. Comput. 19(3), 359–373 (2015)

    Article  Google Scholar 

  9. D. Grochol, L. Sekanina, M. Zadnik, J. Korenek, V. Kosar, Evolutionary circuit design for fast FPGA-based classification of network application protocols. Appl. Soft Comput. 38, 933–941 (2016). doi:10.1016/j.asoc.2015.09.046

    Article  Google Scholar 

  10. V. Gupta, D. Mohapatra, A. Raghunathan, K. Roy, Low-power digital signal processing using approximate adders. IEEE Trans. CAD Integr. Circuits Syst. 32(1), 124–137 (2013)

    Article  Google Scholar 

  11. J. Han, M. Orshansky, in Approximate Computing: An Emerging Paradigm for Energy-Efficient Design. Proceedings of the 18th IEEE European Test Symposium (IEEE, 2013), pp. 1–6

  12. T. Higuchi, T. Niwa, T. Tanaka, H. Iba, H. de Garis, T. Furuya, in Evolving Hardware with Genetic Learning: A First Step Towards Building a Darwin Machine. Proceedings of the 2nd International Conference on Simulated Adaptive Behaviour (MIT Press, Cambridge, 1993), pp. 417–424

  13. R. Hrbacek, in Parallel Multi-objective Evolutionary Design of Approximate Circuits. Proceedings of the 2015 Conference on Genetic and Evolutionary Computation (GECCO ’15) (ACM, 2015), pp. 687–694

  14. R. Hrbacek, L. Sekanina, in Towards Highly Optimized Cartesian Genetic Programming: From Sequential Via SIMD and Thread to Massive Parallel Implementation. Proceedings of the Conference on Genetic and Evolutionary Computation (ACM, 2014), pp. 1015–1022

  15. M. Iqbal, W.N. Browne, M. Zhang, Reusing building blocks of extracted knowledge to solve complex, large-scale Boolean problems. IEEE Trans. Evol. Comput. 18(4), 465–480 (2014)

    Article  Google Scholar 

  16. P. Kaufmann, T. Knieper, M. Platzner, in A Novel Hybrid Evolutionary Strategy and Its Periodization with Multi-objective Genetic Optimizers. IEEE Congress on Evolutionary Computation (CEC) (IEEE, 2010), pp. 1–8

  17. P. Kulkarni, P. Gupta, M.D. Ercegovac, Trading accuracy for power in a multiplier architecture. J. Low Power Electron. 7(4), 490–501 (2011)

    Article  Google Scholar 

  18. J. Lind-Nielsen, H. Cohen, in BuDDy—A Binary Decision Diagram Package. http://sourceforge.net/projects/buddy/

  19. J.F. Miller, Cartesian Genetic Programming (Springer, Berlin, 2011)

    Book  MATH  Google Scholar 

  20. J.F. Miller, S.L. Smith, Redundancy and computational efficiency in cartesian genetic programming. IEEE Trans. Evol. Comput. 10(2), 167–174 (2006)

    Article  Google Scholar 

  21. A. Mishchenko, in ABC: A System for Sequential Synthesis and Verification (Berkeley Logic Synthesis and Verification Group, University of California, Berkeley, CA, US, 2012). http://www.eecs.berkeley.edu/~alanmi/abc/

  22. M. Murakawa, S. Yoshizawa, I. Kajitani, T. Furuya, M. Iwata, T. Higuchi, in Evolvable Hardware at Function Level. Parallel Problem Solving from Nature (PPSN IV). LNCS, vol. 1141 (Springer, Berlin, 1996), pp. 62–71

  23. K. Nepal, Y. Li, R.I. Bahar, S. Reda, in Abacus: A Technique for Automated Behavioral Synthesis of Approximate Computing Circuits. Proceedings of the Conference on Design, Automation and Test in Europe (DATE ’14) (EDA Consortium, 2014), pp. 1–6

  24. R. Poli, J. Page, Solving high-order Boolean parity problems with smooth uniform crossover, sub-machine code GP and demes. Genet. Program. Evol. Mach. 1(1–2), 37–56 (2000)

    Article  MATH  Google Scholar 

  25. A. Sanchez-Clemente, L. Entrena, M. Garcia-Valderas, in Error Masking with Approximate Logic Circuits Using Dynamic Probability Estimations. 20th International On-Line Testing Symposium (IOLTS) (IEEE, 2014), pp. 134–139

  26. L. Sekanina, Z. Vasicek, in Evolutionary Computing in Approximate Circuit Design and Optimization. 1st Workshop on Approximate Computing (WAPCO 2015) (2015), pp. 1–6

  27. A.P. Shanthi, R. Parthasarathi, Practical and scalable evolution of digital circuits. Appl. Soft Comput. 9(2), 618–624 (2009)

    Article  Google Scholar 

  28. E. Stomeo, T. Kalganova, C. Lambert, Generalized disjunction decomposition for evolvable hardware. IEEE Trans. Syst. Man Cybern. Part B 36(5), 1024–1043 (2006)

    Article  Google Scholar 

  29. A. Thompson, P. Layzell, S. Zebulum, Explorations in design space: unconventional electronics design through artificial evolution. IEEE Trans. Evol. Comput. 3(3), 167–196 (1999)

    Article  Google Scholar 

  30. J. Torresen, A scalable approach to evolvable hardware. Genet. Program. Evol. Mach. 3(3), 259–282 (2002)

    Article  MATH  Google Scholar 

  31. Z. Vasicek, in Cartesian GP in Optimization of Combinational Circuits with Hundreds of Inputs and Thousands of Gates. Proceedings of the 18th European Conference on Genetic Programming—EuroGP, LCNS no. 9025 (Springer, Berlin, 2015), pp. 139–150

  32. Z. Vasicek, L. Sekanina, Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware. Genet. Program. Evol. Mach. 12(3), 305–327 (2011)

    Article  Google Scholar 

  33. Z. Vasicek, L. Sekanina, in Evolutionary Design of Approximate Multipliers Under Different Error Metrics. IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (IEEE, 2014), pp. 135–140

  34. Z. Vasicek, L. Sekanina, in How to Evolve Complex Combinational Circuits from Scratch? IEEE International Conference on Evolvable Systems Proceedings (IEEE, 2014), pp. 133–140

  35. Z. Vasicek, L. Sekanina, in Circuit Approximation Using single- and Multi-objective Cartesian GP. Proceedings of the 18th European Conference on Genetic Programming— (EuroGP), LNCS no. 9025 (Springer, Berlin, 2015), pp. 217–229

  36. Z. Vasicek, L. Sekanina, Evolutionary approach to approximate digital circuits design. IEEE Trans. Evol. Comput. 19(3), 432–444 (2015)

    Article  Google Scholar 

  37. Z. Vasicek, L. Sekanina, in Evolutionary Approximation of Complex Digital Circuits. Genetic and Evolutionary Computing Conference (ACM, 2015), pp. 1505–1506

  38. V. Vassilev, D. Job, J.F. Miller, in Towards the Automatic Design of More Efficient Digital Circuits. Proceedings of the 2nd NASA/DoD Workshop on Evolvable Hardware (IEEE Computer Society, Los Alamitos, 2000), pp. 151–160

  39. S. Venkataramani, K. Roy, A. Raghunathan, in Substitute-and-Simplify: A Unified Design Paradigm for Approximate and Quality Configurable Circuits. Design, Automation and Test in Europe (DATE ’13) (EDA Consortium, San Jose, 2013), pp. 1367–1372

  40. S. Venkataramani, A. Sabne, V.J. Kozhikkottu, K. Roy, A. Raghunathan, in SALSA: Systematic Logic Synthesis of Approximate Circuits. The 49th Annual Design Automation Conference (DAC ’12) (ACM, 2012), pp. 796–801

  41. R. Venkatesan, A. Agarwal, K. Roy, A. Raghunathan, in MACACO: Modeling and Analysis of Circuits for Approximate Computing. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (IEEE, 2011), pp. 667–673

  42. C. Yang, M. Ciesielski, BDS: a BDD-based logic optimization system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7), 866–876 (2002)

    Article  Google Scholar 

Download references

Acknowledgments

This work was supported by the Czech science foundation Project 14-04197S.

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Lukas Sekanina.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Vasicek, Z., Sekanina, L. Evolutionary design of complex approximate combinational circuits. Genet Program Evolvable Mach 17, 169–192 (2016). https://doi.org/10.1007/s10710-015-9257-1

Download citation

  • Received:

  • Revised:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10710-015-9257-1

Keywords

Navigation