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A Comparison of Evolvable Hardware Architectures for Classification Tasks

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Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5216))

Abstract

We analyze and compare four different evolvable hardware approaches for classification tasks: An approach based on a programmable logic array architecture, an approach based on two-phase incremental evolution, a generic logic architecture with automatic definition of building blocks, and a specialized coarse-grained architecture with pre-defined building blocks. We base the comparison on a common data set and report on classification accuracy and training effort. The results show that classification accuracy can be increased by using modular, specialized classifier architectures. Furthermore, function level evolution, either with predefined functions derived from domain-specific knowledge or with functions that are automatically defined during evolution, also gives higher accuracy. Incremental and function level evolution reduce the search space and thus shortens the training effort.

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Glette, K., Torresen, J., Kaufmann, P., Platzner, M. (2008). A Comparison of Evolvable Hardware Architectures for Classification Tasks. In: Hornby, G.S., Sekanina, L., Haddow, P.C. (eds) Evolvable Systems: From Biology to Hardware. ICES 2008. Lecture Notes in Computer Science, vol 5216. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-85857-7_3

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  • DOI: https://doi.org/10.1007/978-3-540-85857-7_3

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-85856-0

  • Online ISBN: 978-3-540-85857-7

  • eBook Packages: Computer ScienceComputer Science (R0)

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