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On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming

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Abstract

Evolvable hardware allows the generation of circuits that are adapted to specific problems by using an evolutionary algorithm (EA). Dynamic partial reconfiguration of FPGA LUTs allows making the processing elements (PEs) of these circuits small and compact, thus allowing large scale circuits to be implemented in a small FPGA area. This facilitates the use of these techniques in embedded systems with limited resources. The improvement on resource-efficient implementation techniques has allowed increasing the size of processing architectures from a few PEs to several hundreds. However, these large sizes pose new challenges for the EA and the architecture, which may not be able to take full advantage of the computing capabilities of its PEs. In this article, two different topologies—systolic array (SA) and Cartesian genetic programming (CGP)—are scaled from small to large sizes and analyzed, comparing their behavior and efficiency at different sizes. Additionally, improvements on SA connectivity are studied. Experimental results show that, in general, SA is considerably more resource-efficient than CGP, needing up to 60% fewer FPGA resources (LUTs) for a solution with similar performance, since the LUT usage per PE is 5 times smaller. Specifically, 10 \(\times\) 10 SA has better performance than 5 \(\times\) 10 CGP, but uses 50% fewer resources.

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Notes

  1. PEs might be defined, for instance, at logic gate level (and, or, xor, etc.) to evolve combinational circuits or at the function level (adders, subtracters, shifters, etc.) for other applications such as image/signal processing.

  2. These two terms are the main branches in which EHW can be classified. Evolutionary hardware design is considered as yet another design methodology, based on EAs, that automatically provides a circuit description fulfilling the required specifications; the final solution, usually the fittest circuit, is kept and used to configure/build the final system. By the contrary, adaptive hardware enables the possibility of hardware self-adaptation in reconfigurable systems. Since the EA has to be embedded in the final system and, along with certain self/environment-awareness, autonomous adaptation capabilities (to the inputs, the environment, the specifications and in the presence of faults) are provided so self-adaptive hardware can emerge as long as no human intervention is needed during the adaptation process.

  3. A serious drawback of this reconfiguration strategy is the decreasing number of LUTs with this operating mode: 100% in Virtex-II Pro and around 25% in Virtex-5.

  4. This is scalability from an architectural point of view, which considers both the maximum size of the evolvable processing structures (CGP, SA, etc.) and the maximum number of PEs, for a given set of FPGA resources. Not to be confused with scalability of representation (related to the size of circuits that can be evolved in a reasonable time considering the chromosome representation) and scalability of evaluation (related to how to reduce evaluation time).

  5. Since Virtex-5 devices feature around 60% smaller reconfiguration frames (which is the minimum reconfigurable unit) compared to Zynq-7000, an implementation in this platform would probably increase the reconfiguration time of the SA. This means the 19,000 evaluations reported [26] would be fewer in a Zynq device, but in any case probably well over the 8700 figure.

  6. Smaller implementations of up to 16 \(\times\) 16 PEs have been proven to reach 500 MHz without showing timing errors.

  7. This number of evaluations (\(2^{18}\)) was chosen experimentally as a good tradeoff between filter quality and evolution time, with significantly better results than \(2^{17}\), whereas \(2^{19}\) was only marginally better [25]. Powers of 2 were used because they were more practical for parallelizing and partitioning the EA.

  8. Salt and pepper noise consists in replacing randomly selected pixels (in this case, 20% of them) with black or white pixels.

  9. This behavior is close to the one originally proposed for SA in [19], where a PE could either repeat its input or act in a cascaded manner. Nevertheless, its application to a DPR-based EHW system is novel.

  10. Alternatively, CGP may increase the number of columns to the left a certain PE can access, but this would further increase the multiplexer size and design complexity.

  11. Further experiments have shown that larger arrays eventually outperform small ones with long enough evolution times, which suggests that the culprit for this effect is the excessively large search space for the current EA. Future work may focus on improving this EA in order to achieve better results in a shorter time.

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Acknowledgements

This work was partially supported by the Spanish Ministry of Economy and Competitiveness under the project REBECCA (Reference TEC2014-58036-C4-2-R), and the FPI grant program of said Ministry (Grant No. BES-2012-060459). The LUT-based PEs were originally developed in collaboration with Ing. Roland Dobai, Ph.D., from Brno University of Technology.

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Mora, J., Salvador, R. & de la Torre, E. On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming. Genet Program Evolvable Mach 20, 155–186 (2019). https://doi.org/10.1007/s10710-018-9340-5

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