Abstract
This paper presents a novel approach that utilizes FPGA self-reconfiguration for efficient computation in the context of Genetic Programming (GP). GP involves evolving programs represented as trees and evaluating their fitness, the latter operation consuming most of the time.
We present a fast, compact representation of the tree structures in FPGA logic which can be evolved as well as executed without external intervention. Execution of all tree nodes occurs in parallel and is pipelined. Furthermore, the compact layout enables multiple trees to execute concurrently, dramatically speeding up the fitness evaluation phase. An elegant technique for implementing the evolution phase, made possible by self-reconfiguration, is also presented.
We use two GP problems as benchmarks to compare the performance of logic mapped onto a Xilinx XC6264 FPGA against a software implementation running on a 200 MHz Pentium Pro PC with 64 MB RAM. Our results show a speedup of 19 for an arithmetic intensive problem and a speedup of three orders of magnitude for a logic operation intensive problem.
This work was supported by the DARPA Adaptive Computing Systems Program under contract DABT63-96-C-0049 monitored by Fort Hauchuca. Alessandro Mei is with the Department of Mathematics of the University of Trento, Italy.
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Sidhu, R.P.S., Mei, A., Prasanna, V.K. (1999). Genetic Programming Using Self-Reconfigurable FPGAs. In: Lysaght, P., Irvine, J., Hartenstein, R. (eds) Field Programmable Logic and Applications. FPL 1999. Lecture Notes in Computer Science, vol 1673. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-48302-1_31
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DOI: https://doi.org/10.1007/978-3-540-48302-1_31
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