Date:    Thu, 30 Aug 2001 15:59:01 PDT
To:      Bill LANGDON http://www.cs.ucl.ac.uk/staff/W.Langdon/
From:    Didier Keymeulen
%WBL 5 Feb 2004 fix formating problem reported today by Paul Ortyl

@inproceedings(Miller:1999:eh,
author	= {J. Miller},
title		= {On the Filtering Properties of Evolved Gate Arrays},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {2-11},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {A small gate array is evolved extrinsically to carry out a low pass filtering task defined over fifteen different frequencies. The circuit is evolved by assessing its response digitised sine waves. Two different fitness functions are contrasted. One is based on computing the sum of the absolute differences between the actual response and that desired, the other is defined by examining characteristics of the Discrete Fourier Transform of the output. The gate arrays possess some linear properties, which means that they are capable of filtering composite signals which have not been encountered in training. This includes signals with noise added and with frequencies which are not in the training set.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)


@inproceedings(Levi:1999:eh,
author	= {D. Levi and S. Guccione},
title		= {GeneticFPGA: Evolving Stable Circuits on Mainstream FPGA Devices},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {12-17},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {GeneticFPGA is a Java-based tool for evolving digital circuits on Xilinx XC4000EX(tm) and XC4000XL(tm) devices. Unlike other FPGA architectures popular with Evolutionary Hardware researchers, the XC4000 series architectures cannot accept arbitrary configuration data. Only a small subset of configuration bit patterns will produce operational circuits; other configuration bit patterns produce circuits which are unreliable and may even permanently damage the FPGA device. GeneticFPGA uses novel software techniques to produce legal circuit configurations for these devices, permitting experimentation with evolvable hardware on the larger, faster, more mainstream devices. In addition, these techniques have led to methods for evolving circuits which are neither temperature, voltage, nor silicon dependent. An 8-bit counter and several digital frequency dividers have been successfully evolved using this approach. GeneticFPGA uses Xilinx's JBits(tm) interface to control the generation of bitstream configuration data and the XHWIF portable hardware interface to communicate with a variety of commercially available FPGA-based hardware. GeneticFPGA, JBits, and XHWIF are currently being ported to the Xilinx Virtex(tm) family of devices, which will provide greatly increased reconfiguration speed and circuit density.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)


@inproceedings(Tufte:1999:eh,
author	= {G. Tufte and P. Haddow},
title		= {Prototyping a GA Pipeline for Complete Hardware Evolution},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {18-25},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {In this paper a new approach to evolvable hardware is introduced termed "Complete Hardware Evolution" (CHE). This method differs from Extrinsic and Intrinsic evolution in that the evolution process itself is implemented in hardware. In addition, the evolution process implementation, referred to herein as the GA Pipeline, is implemented on the same chip as the evolving design. A prototype implementation of the GA Pipeline is presented which uses FPGA technology as the implementation medium.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Damiani:1999:eh,
author	= {E. Damiani and A. Tettamanzi and V. Liberali},
title		= {On-line Evolution of FPGA-based Circuits: A Case Study on Hash Functions},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {26-33},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16- bit address space into an 8-bit one. The target technology is FPGA, where the search space of the algorithm is made of the combinational functions computed by cells and of the interconnections among cells. An experimental study is carried out to determine the best set of parameters for on-line execution. It is observed that small population size leads to more effective results when short execution time is required. An application of the evolutionary approach presented in the paper for on-line tuning of the function during cache memory operation is also discussed.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Vassilev:1999:eh,
author	= {V. Vassilev and J. Miller and T. Fogarty},
title		= {On the Nature of Two-Bit Multiplier Landscapes},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {36-45},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {The two-bit multiplier is a simple electronic circuit, small enough to be evolvable, and practically useful for the implementation of many digital systems. In this paper, we study the structure of the two-bit multiplier fitness landscapes generated by circuit evolution on an idealised model of a field-programmable gate array. The two-bit multiplier landscapes are challenging. The difficulty in studying these landscapes stems from the genotype representation which allows us to evolve the functionality and connectivity of an array of logic cells. Here, the genotypes are simply strings defined over two completely different alphabets. This makes the study of the corresponding landscapes much more involved. We outline a model for studying the two-bit multiplier landscapes and estimate the amplitudes derived from the Fourier transform of these landscapes. We show that the two-bit multiplier landscapes can be characterised in terms of subspaces, determined by the interactions between the genotype partitions.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(aguirre:1999:EH,
author	= {A. Hernández-Aguirre and C. Coello and B. Buckles},
title		= {A Genetic Programming Approach to Logic Function Synthesis by means of Multiplexers},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {46-53},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {This paper presents an approach based on the use of genetic programming to synthesize logic functions. The proposed approach uses the 1-control line multiplexer as the only design unit, defining any logic function (defined by a truth table) through the replication of this single unit. Our fitness function first explores the search space trying to find a feasible design and then concentrates in the minimization of such (fully feasible) circuit. The proposed approach is illustrated using several sample Boolean functions.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Kalganova:1999:eh,
author	= {T. Kalganova and J. Miller},
title		= {Evolving More Efficient Digital Circuits by Allowing Circuit Layout Evolution and Multi-Objective Fitness},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {54-63},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {We use evolutionary search to design combinational logic circuits. The technique is based on evolving the functionality and connectivity of a rectangular array of logic cells whose dimension is defined by the circuit layout. The main idea of this approach is to improve quality of the circuits evolved by the genetic algorithm (GA) by reducing the number of active gates used. We accomplish this by combining two ideas: 1) using multi-objective fitness function; 2) evolving circuit layout. It will be shown that using these two approaches allows us to increase the quality of evolved circuits. The circuits are evolved in two phases. Initially the genome fitness in given by the percentage of output bits that are correct. Once 100% functional circuits have been evolved, the number of gates actually used in the circuit is taken into account in the fitness function. This allows us to evolve circuits with 100% functionality and minimise the number of active gates in circuit structure. The population is initialised with heterogeneous circuit layouts and the circuit layout is allowed to vary during the evolutionary process. Evolving the circuit layout together with the function is one of the distinctive features of proposed approach. The experimental results show that allowing the circuit layout to be flexible is useful when we want to evolve circuits with the smallest number of gates used. We find that it is better to use a fixed circuit layout when the objective is to achieve the highest number of 100% functional circuits. The two-fitness strategy is most effective when we allow a large number of generations},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Zebulum:1999:eh,
author	= {R. Zebulum and M. Pacheco and M. Vellasco},
title		= {Artificial Evolution of Active Filters: A Case Study},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {66-75},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {This article focuses on the application of artificial evolution to the synthesis of analog active filters. The main objective of this research is the achievement of a new class of systems, with advantageous features compared to conventional ones, such as lower power consumption and area, higher speed and more robustness to noise. The particular problem of designing the amplifier of an AM receiver is examined in this work. Genetic algorithms are employed as our evolutionary tool and two sets of experiments are described. The first set has been carried out using a single objective, the desired frequency response of the circuit. In a second set of experiments, three other objectives have been included in the system: the minimisation of power consumption; the maximisation of the symmetric excursion in the output; and the minimisation of noise in the amplifier output. A new multi-objective evaluation methodology was conceived for this second set of experiments. A second approach for evolving active filters, using programmable chips, is also discussed in this paper.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Stoica:1999:eh,
author	= {A. Stoica and D. Keymeulen and R. Tawel and C. Salazar-Lazaro and W. Li},
title		= {Evolutionary Experiments with a Fine-Grained Reconfigurable Architecture for Analog and Digital CMOS Circuits},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {76-84},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {The paper describes the architectural details of a fine-grained Programmable Transistor Array (PTA) architecture and illustrates its use in evolutionary experiments on the synthesis of both analog and digital circuits. A PTA chip was built in CMOS to allow circuits obtained through evolutionary design using a simulated PTA to be immediately deployed and validated in hardware and, moreover, enables a benchmarking and comparison of evolutions carried out via simulations only (extrinsic evolution) with the chip-in-the-loop (intrinsic) evolutions. The evolution of an analog computational circuit and a logical inverter are presented. Synthesis by software evolution found several potential solutions satisfying the a-priory constraints; however, only a fraction of these proved valid when ported to the hardware. The circuits evolved directly in hardware proved stable when ported to different chips. In either case, both software and hardware experiments indicate that evolution can be accelerated when gray-scale (as opposed to binary switches) were used to define circuit connectivity. Overall, only evolution directly in hardware appears to guarantee a valid solution.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Layzell:1999:eh,
author	= {P. Layzell},
title		= {Inherent Qualities of Circuits Designed by Artificial Evolution: A Preliminary Study of Populational Fault Tolerance},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {85-86},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {An investigation of the likelihood of evolved circuit populations to contain an individual robust to a fault which renders the previously best individual useless.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Lohn:1999:eh,
author	= {J. Lohn and G. Haith and S. Colombano and D. Stassinopoulos},
title		= {A Comparison of Dynamic Fitness Schedules for Evolutionary Design of Amplifiers},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {87-92},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {High-level analog circuit design is a complex problem domain in which evolutionary search has recently produced encouraging results. However, little is known about how to best structure evolution for these tasks. The choices of circuit representation, fitness evaluation technique, and genetic operators clearly have a profound effect on the search process. In this paper, we examine fitness evaluation by comparing the effectiveness of four fitness schedules. Three fitness schedules are dynamic the evaluation function changes over the course of the run, and one is static. Coevolutionary search is included, and we present a method of evaluating the problem population that is conducive to multiobjective optimization. Twenty-five runs of an analog amplifier design task using each fitness schedule are presented. The results indicate that solution quality is highest with static and coevolving fitness schedules as compared to the other two dynamic schedules. We discuss these results and offer two possible explanations for the observed behavior: retention of useful information, and alignment of problem difficulty with circuit proficiency.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Flockton:1999:eh,
author	= {S. Flockton and K. Sheehan},
title		= {A System for Intrinsic Evolution of Linear and Non-linear Filters},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {93-100},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {A system for exploring intrinsic evolution of linear and non-linear filter systems is described. It consists of a testbed topology of operational amplifiers and linear or non-linear passive components together with a control and measurement system for selecting different values and layouts of components and testing the resulting circuit. The results of each measurement can be used by an evolutionary algorithm to search for a good match to a target response.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(deGaris:1999:eh,
author	= {H. {de Garis} and A. Buller and M. Korkin and F. Gers and N. Nawa and M. Hough},
title		= {ATR's Artificial Brain ("CAM-Brain") Project: A Sample of what Individual "CoDi-1Bit" Model Evolved Neural Net Modules can do with Digital and Analog I/O},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {102-110},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {This work presents a sample of what evolved neural net circuit modules using the socalled "CoDi-1Bit" neural net model [5] can do. This work is part of an 8 year research project at ATR which aims to build an artificial brain containing a billion neurons by the year 2001, that will be used to control the behaviors of a kitten robot "Robokoneko" [2][3][4]. It looks as though the figure is more likely to be 40 million, but the numbers are not of great concern. What is more important is the issue of evolvability of the cellular automata (CA) based neural net circuits which grow and evolve in special FPGA (Field Programmable Gate Array) hardware, at hardware speeds (e.g. updating 150 billion CA cells per second, and performing a complete run of a genetic algorithm, i.e. tens of thousands of circuit growths and fitness evaluations, to evolve the elite neural net circuit in about 1 second). The specialized hardware which performs this evolution is labeled the CAM-Brain Machine (CBM) [6]. It implements the CoDi-1Bit model, and was delivered to ATR in May 1999. The CBM should make practical the assemblage of 10,000s of evolved neural net modules into humanly defined artificial brain architectures. For the past few months, the latest hardware version of the CBM has been simulated in software to see just how evolvable and functional individual evolved modules can be. This work reports on some of the results of these simulations, for which the input/output is either binary or analog.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Vassilev:1999:eh,
author	= {V.Vassilev and J. Miller and T. Fogarty},
title		= {Co-evolving Demes of Non-uniform Cellular Automata for Synchronisation},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {111-119},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {Emergent computation refers to systems in which global information processing appears as a result of the interactions among many components, each of which may be a system that exhibits an ability for emergent computation at a different level of self-organisation. In this paper, we employ a modification of cellular programming to evolve cellular machines for synchronisation. This allows global computation to occur by many local interactions among computational demes of interacting cells. The computational machine, derived from the non-uniform cellular automata model, consists of a grid of cells which are co-evolved in isolated demes. We describe experiments which show that demes can be co-evolved to perform non-trivial computation. We also analyse the mechanisms of computation within the different synchronising demes. Our results not only show that the co-evolution of demes is possible, but that they can attain high computational performance through co-operative action.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Ortega:1999:eh,
author	= {C. Ortega and A. Tyrrell},
title		= {Reliability Analysis in Self-Repairing Embryonic Systems},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {120-128},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {One characteristic of biological organisms that is desirable in engineering systems is the ability to tolerate faults in their components. Fault tolerance in artificial cellular systems is generally achieved by either time-redundancy or hardware-redundancy. In hardware redundancy spare cells are introduced so that when an active cell fails, a spare substitutes it. In the embryonic hardware architecture designed at York, this hardware redundancy is achieved in a multi-cellular system inspired by cell embryology. In this paper the k-out-of-m reliability model is used to analyse the reconfiguration strategies used in embryonic arrays. Two schemes are investigated: row-( or column-) elimination and cell-elimination. The models proposed can be used to analyse the reliability of cellular systems with spares other than embryonic arrays.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Perkowski:1999:eh,
author	= {M. Perkowski  and A. Chebotarev and A. Mishchenko},
title		= {Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {129-138},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {Here we advocate an approach to learning hardware based on induction of finite state machines from temporal logic constraints. The method involves training on examples, constraints solving, determinization, state machine minimization, structural mapping, functional decomposition of multi-valued logic functions and relations, and finally, FPGA mapping. In our approach, learning takes place on the level of constraint acquisition and functional decomposition rather than on the lower level of programming binary switches. Our learning strategy is based on the principle of Occam's Razor, facilitating generalization and discovery. We implemented several learning algorithms using DEC-PERLE-1 FPGA board.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Mjolsness:1999:eh,
author	= {E. Mjolsness  and E. Meyerowitz and V. Gor and T. Mann},
title		= {Morphogenesis in Plants: Modeling the Shoot Apical Meristem, and Possible Applications},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {139-144},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {A key determinant of overall morphogenesis in flowering plants such as Arabidopsis thaliana is the shoot apical meristem (growing tip of a shoot). Gene regulation networks can be used to model this system. We exhibit a very preliminary two-dimensional model including gene regulation and intercellular signaling, but omitting cell division and dynamical geometry. The model can be trained to have three stable regions of gene expression corresponding to the central zone, peripheral zone, and rib meristem. We also discuss a space-engineering motivation for studying and controlling the morphogenesis of plants using such computational models.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Davis:1999:eh,
author	= {P. Davis},
title		= {Adaptive Networks with Self-Organizing Multi-Hop Links},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {145-150},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {A method is proposed for adapting transmissions in a network so that multi-hop paths form to link nodes emitting compatible signal types. The method uses a simple, local adaptation of transmission weights at each node depending only on the signals passing through the node. This method is applicable for autonomous organization of functions in ad-hoc distributed systems mediated by communication.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Lu:1999:eh,
author	= {G. Lu and H. Singh and M. Lee and N. Bagherzadeh and F. Kurdahi and E. Filho and V. Castro-Alves},
title		= {The MorphoSys Dynamically Reconfigurable System-On-Chip},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {152-160},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {MorphoSys is a system-on-chip which combines a RISC processor with an array of reconfigurable cells. The important features of MorphoSys are coarse-grain granularity, dynamic reconfigurability and considerable depth of programmability. The first implementation of the MorphoSys architecture, the M1 chip, is currently at an advanced stage and it will operate at 100 MHz. Simulation results indicate significant performance improvements for different classes of applications, as compared to general-purpose processors. Meanwhile, MorphoSys can provide the potential hardware platform for the evolvable hardware(EH) simulation with the help of the software.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Milne:1999:eh,
author	= {G. Milne},
title		= {A Model for Dynamic Adaptation in Reconfigurable Hardware Systems},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {161-169},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {A theory is presented in which to model the changing structure found in reconfigurable computing devices and which provides a foundation for developing the languages necessary to program such devices. The core concept is that of a complex system of agents which interact with each other over a changing, connective topological structure. The agents themselves may be created, destroyed and evolve in a biological- like manner. These concepts and the manner in which they are harnessed within the dsCircal model are presented in this paper. The relationship between these concepts and reconfigurable evolvable hardware is outlined, giving a basis for a compilation mechanism allowing the high-level programming of dynamically changing hardware systems.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Porter:1999:eh,
author	= {R. Porter and K. McCabe and N. Bergmann},
title		= {An Applications Approach to Evolvable Hardware},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {170-174},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {We discuss the use of Field Programmable Gate Arrays (FPGAs) as hardware accelerators in genetic algorithm (GA) applications. The research is particularly focused on image processing optimization problems where fitness evaluation is computationally demanding and poorly suited to micro-processor systems. This research identifies key design principles for FPGA based GA and suggests a novel 2 stage reconfiguration technique. We demonstrate its effectiveness in obtaining significant speed-up; and illustrate the unique hardware GA design environment where representation is driven by a combination of hardware architecture and problem domain.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Macias:1999:eh,
author	= {N. Macias},
title		= {The PIG Paradigm: The Design and Use of a Massively Parallel Fine Grained Self-Reconfigurable Infinitely Scalable Architecture},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {175-180},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {The requirements of a general purpose massively parallel processing system are outlined. The suitability of a fine-grained self-reconfigurable system to general massively parallel processing is shown. A new type of self-reconfigurable device called the PIG is introduced, and details of its design and operation are explained. The PIG's uniqueness compared to other reconfigurable systems is discussed. This uniqueness is further illustrated through specific examples of PIG circuits. An application of the PIG to evolvable hardware is described. Further potential applications are discussed. Plans for future work, including options for building a large-scale PIG are discussed.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Moreno:1999:eh,
author	= {J. Moreno and J. Madrenas and J. Cabestany and E. Canto and R. Kielbik and J. Faura and J. Insenser},
title		= {Realization of Self-Repairing and Evolvable Hardware Structures by Means of Implicit Self-Configuration},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {182-187},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {In this paper we shall address the physical implementation of self-repairing and evolvable hardware strategies. These alternatives will be enabled by the specific dynamic reconfiguration capabilities included in a new family of FPGA devices, called FIPSOC (Field Programmable System On a Chip). The main features of these devices are given by the integration on a single chip of a dynamically reconfigurable FPGA, a programmable analog section and a microcontroller. As our experimental results will show, the efficient use of the available resources makes these devices an excellent platform for testing, developing and realizing physically new concepts in electronic design.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(McDonald:1999:eh,
author	= {J. McDonald and B. Goda},
title		= {Reconfigurable FPGA's in the 1-20 GHz Band with HBT BiCMOS},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {188-192},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {This paper describes the operation of a field programmable gate array (FPGA), the basics of current mode logic, and examines the idea of creating a SiGe heterojunction bipolar (HBT) version of the Xilinx 6200 FPGA. A new proposed device would be bitwise compatible with the 6200, but would operate in the 1-20 GHz range due to the HBT technology being used for the logic and routing and CMOS for storing the configuration bits. This is possible due to the IBM cointegration process of a HBT with a BiCMOS process. Information in this paper is based on an HBT having a fT of 50 GHz, but later in 1999 IBM will be unveiling a process that will double the speed.

By replacing and redesigning key parts of the 6200 FPGA, a 100-200X operating speedup is possible. The core logic cell in the 6200 consists of two input multiplexers and flip-flops, which can easily be converted to current mode logic (CML). Routing in a conventional FPGA is done via pass transistors, which can act like a low pass filter for a high-speed signal. A SiGe HBT CML multiplexer can be used for routing, which can pass signals with a 12-14 picoseconds delay. Through the use of a side decoder, memory planes of configuration could be used to store current and future configurations. Interchange could occur between memory planes if the old flip-flop values are stored, new flip-flop values are restored, and then the new configuration plane is activated. Countless applications such as DSP, Ethernet routing, missile control, and artificial intelligence could utilize a SiGe HBT FPGA.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Asari:1999:eh,
author	= {K. Asari and Y. Mitsuyama and T. Onoye and I. Shirakawa and H. Hirano and T. Honda and T. Otsuki and T. Baba and T. Meng},
title		= {FeRAM Circuit Technology for System on a Chip},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {193-199},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {The ferroelectric memory (FeRAM) has a great advantage for system on a chip, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM. To enhance the applicability of FeRAM for embedded reconfigurable hardware, three circuit technologies are discussed in this paper. Simulation and measurement data confirmed that both power consumption and memory area can be substantially reduced, making FeRAM the most promising new technology for implementing high-performance, low-power reconfigurable hardware.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Crossley:1999:eh,
author	= {W. Crossley},
title		= {Optimization for Aerospace Conceptual Design through the use of Genetic Algorithms},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {200-207},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {Using a Genetic Algorithm (GA) as a non-calculus-based global search method allows optimization-like techniques to be applied in the conceptual phase of design, which traditionally has been dominated by qualitative or subjective decision making. Features of the GA provide several advantages for conceptual design including: the ability to combine discrete, integer and continuous variables, the population-based search, no requirement for an initial design, and the ability to address non-convex, multimodal and discontinuous functions. Examples of applications to aerospace system conceptual design include aerospace vehicle design and satellite constellation design. A multiobjective design approach using the GA is also discussed.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Pollack:1999:eh,
author	= {J. Pollack and H. Lipson and P. Funes and S. Ficici and G. Hornby},
title		= {Coevolutionary Robotics},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {208-216},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {We address the fundamental issue of fully automated design (FAD) and construction of inexpensive robots and their controllers. Rather than seek an intelligent general purpose robot - the humanoid robot, ubiquitous in today's research as the long term goal - we are developing the information technology that can design and fabricate special-purpose mechanisms and controllers to achieve specific short-term objectives. These robots will be constructed from reusable sensors, effectors, and computers held together with materials custom "printed" by rapid prototyping (RP) equipment. By releasing the goal of designing software controllers for EXISTING machines in favor of the automated co-design of software and hardware together, we will be replicating the principles used by biology in the creation of complex groups of animals adapted to specific environments.

Programming control software has become so difficult as more degrees of freedom and task goals are added to robots, that the most advanced ones do not get past the stage of teleoperation or choreographed behavior. In other words, they are puppets, not robots. Our primary hypothesis is that the reason current approaches to robotics often fail is because of an underestimation of the complexity of the software design problem. Traditionally, engineers will build a complex robot, complete with powerful motors and sensors, and leave for the control programmers to write a program to make it run. But if we look into nature, we see animal brains of very high complexity, at least as complex as the bodies they inhabit, which have been precisely selected to be controllable. New sensor and effector technology - for example, the micromotor, the optical position sensor, memory wire, FPGA's, biomimetic materials, biologically inspired retinas, and lately, MEMS, despite radical claims, cannot produce the desired breakthroughs. True robot success is task specific, not general purpose, and would be recognizable even if built of old electromechanical components.

In nature, the body and brain of a horse are tightly coupled, the fruit of a long series of small mutual adaptations - neither one was first. Today's horse brain was lifted, 99.9% complete, from the animal that preceded it. There is never a situation in which the hardware has no software, or where a growth or mutation - beyond the adaptive ability of a brain - survives. This chicken-egg problem of body-brain development is best understood as a form of co-evolution - agents learning in environments that respond to the agents by creating more challenging and diverse tasks.

By using a combination of commercial off-the-shelf (COTS) CAD/CAM simulation software and our own physical simulators constrained to correspond to real physical devices, we have been developing the technology for the coevolution of body and brains: adaptive learning in body simulations, and the migration of "brains" from simpler to more complex simulated bodies until the virtual robot steps into reality using extensions of today's rapid prototyping technology. Finally, the robot's brains must be robust enough to learn how to bridge the transition from virtual to actual reality.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Haupt:1999:eh,
author	= {R. Haupt and J. Johnson},
title		= {Dynamic Phase-Only Array Beam Control using a Genetic Algorithm},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {217-224},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {This paper describes two approaches to evolvable antenna array beams. The first approach uses a genetic algorithm for adaptive phase-only nulling with phased arrays. A genetic algorithm adjusts some of the least significant bits of the beam steering phase shifters in order to minimize the total output power. Using a few bits for nulling speeds convergence of the algorithm and limits pattern distortions. Various results are presented to show the advantages and limitations of this approach. A second problem is a switched beam linear array in which two beams with specified shapes, a narrow beam and a wide beam, are to be produced. The goal of the design effort is to determine a set of complex excitation coefficients such that switching between beams is accomplished by changes in the phase weights alone. Excellent results are obtained by simultaneous, multi-objective optimization based design using a GA instead of sequential a GA optimization for the narrow and wide beam cases individually.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Linden:1999:eh,
author	= {D. Linden and E. Altshuler},
title		= {Evolving Wire Antennas using Genetic Algorithms: A Review},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {225-232},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {Communication, radar and remote sensing systems employ thousands of different types of wire antennas, and there is an increasing need for high-performance, customized antennas. Current methods of designing and optimizing them by hand using simulation or analysis are time- and labor-intensive, limit complexity, increase the cost and time expended, and require that antenna engineers have significant knowledge of the universe of antenna designs. Local optimization methods are not much better, since an initial guess that is close to the final design must be provided. Using a genetic algorithm (GA), it is possible to prescribe the desired performance of an antenna and allow the computer to find the parameters for the design. The GA does not require an initial guess, and the amount of design information the engineer must supply can be very minimal. This paper will present a review of a few wire antennas from previous publications [1-5] designed by GA for unconventional purposes. This approach has the potential to revolutionize antenna design.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Avizienis:1999:eh,
author	= {A. Avizienis},
title		= {The Hundread Year Spacecraft},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {233-239},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {Two major steps in the evolution of autonomous, long-life spacecraft computing systems have been the demonstrations of systems with one-year and ten-year life expectancies in space. This paper discusses the design concept of a distributed, diversified self-testing and self-repairing computing system that is embedded in an autonomous spacecraft and serves as its agent for automatic maintenance. The attainment of a hundred-year life expectancy is founded on the extensive use of diversity in materials, technologies and design of hardware elements. Diversity of hardware and software designs also provides tolerance of design faults. A hierarchical system structure and a rigorous design paradigm for the fault-tolerance defenses also support the goals of autonomy and long system lifetime.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Cwik:1999:eh,
author	= {T. Cwik and G. Klimeck},
title		= {Genetically Engineered Microelectronic Infrared Filters},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {242-246},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {A genetic algorithm is used for design of infrared filters and in the understanding of the material structure of a resonant tunneling diode. These two components are examples of microdevices and nanodevices that can be numerically simulated using fundamental mathematical and physical models. Because the number of parameters that can be used in the design of one of these devices is large, and because experimental exploration of the design space is unfeasible, reliable software models integrated with global optimization methods are examined. The genetic algorithm and engineering design codes have been implemented on massively parallel computers to exploit their high performance. Design results are presented for the infrared filter showing new and optimized device design. Results for nanodevices are presented in a companion paper at this workshop.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Klimeck:1999:eh,
author	= {G. Klimeck and C. Salazar-Lazaro and A. Stoica and T. Cwik},
title		= {"Genetically Engineered" Nanoelectronics},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {247-248},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {The quantum mechanical functionality of nanoelectronic devices such as resonant tunneling diodes (RTDs), quantum well infrared photodetectors (QWIPs), quantum well lasers, and heterostructure field effect transistors (HFETs) is enabled by material variations on an atomic scale. The design and optimization of such devices requires a fundamental understanding of electron transport in such dimensions. The Nanoelectronic Modeling Tool (NEMO) is a general-purpose quantum device design and analysis tool based on a fundamental non-equilibrium electron transport theory. NEMO was combined with a parallelized genetic algorithm package (PGAPACK) to evolve structural and material parameters to match a desired set of experimental data. A numerical experiment that evolves structural variations such as layer widths and doping concentrations is performed to analyze an experimental current voltage characteristic. The genetic algorithm is found to drive the NEMO simulation parameters close to the experimentally prescribed layer thicknesses and doping profiles. With such a quantitative agreement between theory and experiment design synthesis can be performed.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(vanRemortel:1999:eh,
author	= {P. {van Remortel} and T. Lenaerts and B. Manderick},
title		= {The Evolution of ROBDDs: Preliminary Results and a First Analysis},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {249-254},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {In this paper we experiment with the use of Reduced and Ordered Binary Decision Diagrams (ROBDDs) as a possible representation for evolving Boolean functions in the context of evolvable hardware. A number of test functions were evolved using ROBDDs. In order to obtain solutions more easily and with lower complexity, we experimented with the use of cube transformations on the target functions. Although the setup still needs tuning, we argue that the use of domain transformations combined with GAs has potential in EHW applications.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Masner:1999:eh,
author	= {J. Masner and J. Cavalieri and J. Frenzel and J. Foster},
title		= {Representation and Robustness for Evolved Sorting Networks},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {255-261},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {We describe evolved sorting networks for a Xilinx 6200 rapidly reconfigurable Field Programmable Gate Array (FPGA) and for a simulated environment. Our goal was to evaluate the efficiency and stability of evolved circuits in a changing environment. Not only did we evolve correct sorting networks, but we also examined the representations of evolved individuals for their runtime efficiency and effectiveness. We compared three different hardware representations: tree structured encodings, linear direct encodings, and raw configuration files. We also used three separate fitness functions.

We also present an interesting metric for gate-level resilience to faults: bitwise stability. We find evidence that evolution inherently improves bitwise stability, and that tree structures may confer more bitwise stability than linear structured chromosomes.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)

@inproceedings(Chongstitvatana:1999:eh,
author	= {P. Chongstitvatana and C. Aporntewan},
title		= {Improving Correctness of Finite-State Machine Synthesis from Multiple Partial Input/Output Sequences},
booktitle	= {The First NASA/DoD Workshop on Evolvable Hardware},
year		= 1999,
editor		= {Adrian Stoica and Jason Lohn and Didier Keymeulen},
pages	= {255-261},
address		= {Pasadena, California},
publisher_address	= {1730 Massachusetts Avenue, N.W., Washington, DC 20036-1992, USA},
month	= {19-21 July},
organization	= {Jet Propulsion Laboratory, California Institute of Technology},
publisher	= {IEEE Computer Society},
note		= {},
%email		= {},
keywords	= {},
ISBN		= {0-7695-0256-3},
url		= {},
size		= {},
abstract	= {Our previous work focused on the synthesis of sequential circuits based on a partial input/output sequence. As the behavioural description of the target circuit is not known the correctness of the result can not be verified. This paper proposes a method which increases the correctness percentage of the finite-state machine (FSM) synthesis using multiple partial input/output sequences. The synthesizer is based on Genetic Algorithm. The experimental results show that the correctness percentage can be increased to 100% by increasing of the number of input/output sequences.},
notes		= {EH1999 http://cism.jpl.nasa.gov/events/nasa_eh/}
)