Sintesis booleanacon programacion genetica paralela en CPU y GPU

Created by W.Langdon from gp-bibliography.bib Revision:1.8612

@Article{Pedraza_Oyaga_Gomez_2013,

• author = "Cesar A. Pedraza and Jaime V. Oyaga and Ricardo C. Gomez",
• title = "Sintesis booleanacon programacion genetica paralela en {CPU y GPU}",
• title_en = "Genetic parallel programing-based Boolean synthesis with CPU and GPU",
• journal = "Ingenium Revista de la facultad de ingenieria",
• year = "2013",
• volume = "14",
• pages = "117--130",
• month = "ene.",
• keywords = "genetic algorithms, genetic programming, Programacion paralela, sintesis booleana, GPU, algoritmo evolutivo, Parallel programming, Boolean synthesis, GPU, evolutionary algorithm",
• URL = "https://revistas.usb.edu.co/index.php/Ingenium/article/view/1325/1116",
• URL = "https://revistas.usb.edu.co/index.php/Ingenium/article/view/1325",
• DOI = "10.21500/01247492.1325",
• size = "14 pages",
• resumen = "La sintesis booleana o combinacional es un proceso mediante el cual se optimiza una red de puertas logicas, con el fin de reducir su consumo, minimizar costos, minimizar area y aumentar el rendimiento a la hora de ser implementada. Por otra parte, la programacion genetica es una alternativa importante para generar estructuras de hardware interesantes y eficientes. Se ha demostrado que los algoritmos evolutivos (AE) tienen mejor rendimiento si se implementan en sistemas paralelos. Este articulo presenta la implementacion de un algoritmo genetico paralelo (PGP) para realizar sintesis booleana en una plataforma basada en CPU-GPU. Esta implementacion emplea el modelo de islas, el cual permite la evolucion paralela e independiente del PGP a traves de las multiples unidades de procesamiento de la GPU y los multiples nucleos de un procesador de ultima generacion. Se probaron diferentes alternativas de mapeo del PGP en la plataforma en orden de optimizar el tiempo de respuesta. Como resultado se muestra una aceleracion superior a 41.",
• abstract = "The Boolean or combinational synthesis is a process that optimizes a logic gates net-work, in order to reduce power consumption, minimize costs, minimize area and increase the performance when it is implemented. Moreover genetic programming is an important alternative to generate interesting and efficient hardware structures. It has been shown that evolvable algorithms are faster when implemented in parallel systems. This paper presents the implementation of a parallel genetic programming (PGP) for boolean synthesis on a GPU-CPU based platform. Our implementation uses the island mode which allows the parallel and independent evolution of the PGP through the multiple processing units of the GPU and the multiple cores of a new generation desktop processors. We tested multiple mapping alternatives of the PGP on the platform in order to optimize the PGP response time. As a result we show that our approach achieves a speedup up to 41.",
• notes = "in spanish

  Universidad Santo Tomas",

}

Genetic Programming entries for Cesar A Pedraza Jaime V Oyaga Ricardo C Gomez

Citations