- author = "Fabian Ritter and Sebastian Hack",
- title = "{PMEvo}: Portable Inference of Port Mappings for out-of-Order Processors by Evolutionary Optimization",
- booktitle = "Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation",
- year = "2020",
- series = "PLDI 2020",
- pages = "608--622",
- address = "London, UK",
- publisher = "Association for Computing Machinery",
- keywords = "genetic algorithms, genetic programming, SBSE, parallel computing, port mapping, evolutionary algorithm, processor reverse engineering",
- isbn13 = "9781450376136",
-
URL = "
https://arxiv.org/abs/2004.10044",
-
URL = "https://doi.org/10.1145/3385412.3385995",
-
DOI = "
doi:10.1145/3385412.3385995",
- size = "15 pages",
-
abstract = "Achieving peak performance in a computer system
requires optimisations in every layer of the system, be
it hardware or software. A detailed understanding of
the underlying hardware, and especially the processor,
is crucial to optimize software. One key criterion for
the performance of a processor is its ability to
exploit instruction-level parallelism. This ability is
determined by the port mapping of the processor, which
describes the execution units of the processor for each
instruction.
Processor manufacturers usually do not share the port mappings of their microarchitectures. While approaches to automatically infer port mappings from experiments exist, they are based on processor-specific hardware performance counters that are not available on every platform.
We present PMEvo, a framework to automatically infer port mappings solely based on the measurement of the execution time of short instruction sequences. PMEvo uses an evolutionary algorithm that evaluates the fitness of candidate mappings with an analytical throughput model formulated as a linear program. Our prototype implementation infers a port mapping for Intel's Skylake architecture that predicts measured instruction throughput with an accuracy that is competitive to existing work. Furthermore, it finds port mappings for AMD's Zen+ architecture and the ARM Cortex-A72 architecture, which are out of scope of existing techniques.",
- notes = "is this GP? cited by mendis-thesis.pdf MIT 2020",
