Circuit segmentation using GP in FPGA's technology mapping
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gp-bibliography.bib Revision:1.7954
- @InProceedings{Srivastava:2016:INDIACom,
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author = "Atul K. Srivastava and Himanshu Shishodia and
Himanshu Jaypee",
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booktitle = "2016 3rd International Conference on Computing for
Sustainable Global Development (INDIACom)",
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title = "Circuit segmentation using {GP} in {FPGA's} technology
mapping",
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year = "2016",
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pages = "1947--1951",
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month = mar,
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publisher = "IEEE",
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address = "New Delhi, India",
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keywords = "genetic algorithms, genetic programming, EHW,
technology mapping, circuit segmentation, FPGA",
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isbn13 = "978-1-4673-9417-8",
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URL = "http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=7724605",
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size = "5 pages",
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abstract = "In this paper an algorithm for efficient technology
mapping in FPGAs using circuit segmentation is proposed
and implemented. In this paper area minimization of the
circuit along with the optimal use of Table Look Ups
(TLU) in the existing library, with minimum redundancy
is discussed. The algorithm has been tested on ISCAS'85
bench mark and other circuits. The results show
considerable improvement in the technology mapping with
respect to area optimisation of the circuit minimised
redundancy.",
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notes = "Also known as \cite{7724605}",
- }
Genetic Programming entries for
Atul K Srivastava
Himanshu Shishodia
Himanshu Jaypee
Citations