Towards the Automatic Design of More Efficient Digital Circuits
Created by W.Langdon from
gp-bibliography.bib Revision:1.8098
- @InProceedings{Vassilev:2000:eh2,
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author = "Vesselin K. Vassilev and Dominic Job and
Julian F. Miller",
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title = "Towards the Automatic Design of More Efficient Digital
Circuits",
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booktitle = "The Second NASA/DoD workshop on Evolvable Hardware",
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year = "2000",
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editor = "Jason Lohn and Adrian Stoica and Didier Keymeulen",
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pages = "151--160",
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address = "Palo Alto, California",
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publisher_address = "1730 Massachusetts Avenue, N.W., Washington, DC,
20036-1992, USA",
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month = "13-15 " # jul,
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organisation = "Jet Propulsion Laboratory, California Institute of
Technology",
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publisher = "IEEE Computer Society",
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keywords = "genetic algorithms, genetic programming",
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ISBN = "0-7695-0762-X",
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DOI = "doi:10.1109/EH.2000.869353",
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abstract = "We introduce a new methodology of evolving electronic
circuits by which the process of evolutionary design is
guaranteed to produce a functionally correct solution.
The method employs a mapping to represent an electronic
circuit on an array of logic cells that is further
encoded within a genotype. The mapping is many-to-one
and thus there are many genotypes that have equal
fitness values. Genotypes with equal fitness values
define subgraphs in the resulting fitness landscapes
referred to as neutral networks. This is further used
in the design of a neutral network that connects the
conventional with other more efficient designs. To
explore such a network a navigation strategy is defined
by which the space of all functionally correct circuits
can be explored. We show that very efficient digital
circuits can be obtained by evolving from the
conventional designs. Results for several binary
multiplier circuits such as the three and four-bit
multipliers are reported. The evolved solution for the
three-bit multiplier consists of 23 two-input logic
gates that in terms of number of two-input gates used
is 23: 3 percentages more efficient than the most
efficient known conventional design. The logic
operators required to implement this circuit are 14
ANDs, 9 XORs, and 2 inversions (NOT). The evolved
four-bit multiplier consists of 57 two-input logic
gates that are 10: 9 percentages more efficient (in
terms of number of two-input gates used) than the most
efficient known conventional design. The optimal size
of the target circuits is also studied by measuring the
length of the neutral walks from the obtained
designs.",
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notes = "EH2000
http://ic-www.arc.nasa.gov/ic/eh2000/index.html",
- }
Genetic Programming entries for
Vesselin K Vassilev
Dominic Job
Julian F Miller
Citations