Mutual Error Compensation based Area and Power efficient Approximate Multiplier

Created by W.Langdon from gp-bibliography.bib Revision:1.7650

@InProceedings{Zhang:2021:ASICON,

• author = "Renyuan Zhang and Xuetao Wang and Ziyu Wang and Anfeng Xue and Haichuan Yang and Yu Gong and Bo Liu2",
• booktitle = "2021 IEEE 14th International Conference on ASIC (ASICON)",
• title = "Mutual Error Compensation based Area and Power efficient Approximate Multiplier",
• year = "2021",
• abstract = "Approximate computing (AC) has now become a popular solution in deploying Neural Network (NN) on hardware to reduce the power consumption. In this paper, the Cartesian Genetic Programming (CGP)-based approximate multiplier and a deliberately designed approximate adders are combined, and a Mutual Error Compensation (MEC) design scheme is proposed to construct a higher-order multiplier. The Penalty Coefficient is introduced in the fitness function of CGP to compensate the error of the next stage approximate addition. The proposed approximate multiplier can achieve power savings of 53.0percent and area savings of 58.7percent comparing to the exact multiplier. Also, it shows the superiority in power consumption and area compared to the state-of-the-art approximate multipliers. The proposed multiplier is also evaluated in a CNN-based keyword spotting (KWS) system, with little accuracy loss and high efficiency.",
• keywords = "genetic algorithms, genetic programming, cartesian genetic programming, Power demand, Conferences, Approximate computing, Error compensation, Artificial neural networks, Hardware",
• DOI = "doi:10.1109/ASICON52560.2021.9620312",
• ISSN = "2162-755X",
• month = oct,
• notes = "Also known as \cite{9620312}",

}

Genetic Programming entries for RenYuan Zhang XueTao Wang Ziyu Wang AnFeng Xue Haichuan Yang Yu Gong Bo Liu2

Citations