- author = "Yang Zhang4 and Qingwen Wei and Hao Cai and Bo Liu2",
- title = "An Energy-Efficient Multiplier Using Hybrid Approximate Logic Synthesis for Mixed-Quantization {CNNs}",
- booktitle = "2024 2nd International Symposium of Electronics Design Automation (ISEDA)",
- year = "2024",
- pages = "229--234",
- month = may,
- keywords = "genetic algorithms, genetic programming, Cartesian Genetic Programming, Industries, Accuracy, Quantization (signal), Power demand, Neural networks, Energy efficiency, Approximate logic synthesis, Re-partition XOR-BMF, Hybrid ALS Flow, Approximate multiplier, Mixed-precision quantization, ANN",
-
DOI = "
doi:10.1109/ISEDA62518.2024.10617603",
- abstract = "Approximate computing is an emerging paradigm that, by relaxing the requirement for full accuracy in convo-lutional neural networks (CNNs), offers benefits in the design area and power consumption. In circuit design, approximate logic synthesis (ALS) is to discover and synthesise the approx-imate circuits automatically, given an exact circuit description. This paper proposes a Hybrid ALS Flow which composes Re-partition XOR-BMF ALS and Cartesian Genetic Programming ALS (CGP-based ALS), and designs the Hessian-aware Mixed-quantization CNNs. This paper designs an 8-bit approximate multiplier using the proposed Hybrid ALS Flow and applies it to the Mixed-quantization CNNs. Experiments show that the proposed Re-partition XOR-BMF ALS has better design space exploration than the BLASYS. Compared to the exact Multiplier, the designed approximate multiplier reduces the power delay product (PDP) by 56.17percent under an industry 28nm process technology with the power supply of O.8V, while the accuracy loss is only 1.33percent and 2.36percent in VGG16 and Resnet50 on CIFARI00.",
-
notes = "Also known as \cite{10617603}
School of Integrated Circuits, Southeast University, Nanjing, China",
