- author = "Jie Chen",
- title = "Next Generation Hardware Monitoring Infrastructure for Multi-core Resource Auditing",
- school = "The School of Engineering and Applied Science of The George Washington University",
- year = "2015",
- address = "USA",
- month = "17 " # may,
- keywords = "genetic algorithms, genetic programming, optimization, security, debugging, power, profiling, energy, CSPPV, CDDG, Fmm, Cholesky, L2 cache, SPEC2k6, SPLASH-2, PARSEC-1.0, ASGP, SESC, Intel Core i7, CC-Auditor",
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URL = "
https://scholarspace.library.gwu.edu/concern/gw_etds/qz20ss512",
-
URL = "https://scholarspace.library.gwu.edu/etd/qz20ss512",
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URL = "https://scholarspace.library.gwu.edu/concern/parent/qz20ss512/file_sets/6969z0774",
-
URL = "https://scholarspace.library.gwu.edu/downloads/6969z0774?disposition=inline&locale=en",
- size = "122 pages",
-
abstract = "Thesis Statement: Performance counters in hardware
have been very successful in providing feedback about
application performance to programmers and compilers.
With the growing relevance of understanding power,
energy and security (information leakage), we envision
that the next generation hardware monitoring
infrastructure will support these features. In this
work, we study the design and implementation of such
hardware monitors.
Continuous advances in semiconductor technologies have enabled the integration of billions of transistors in modern multicore processors. This offers software applications with abundant hardware resources to use. To realize more parallelism and higher performance, software developers are concerned about characterizing and optimizing their applications over the usage of hardware resources. At the same time, hardware monitoring infrastructure in most current processors offers a collection of hardware counters for auditing architectural events on hardware units. Such counters can be used by programmers and performance analysts for auditing performance bottlenecks and consequently, optimizing application performance. In recent years, there is a surging demand for improving application power, energy and information leakage beyond performance, due to the increasing complexity in power delivery inside the processor chip and the vast amount of shared hardware resources.
As power budget is limited, it becomes necessary to audit software power usages and look for power optimization at all levels to better use the limited power. Optimizing the applications for energy is necessary due its impact to the operational cost in the system. Inefficient software has been often cited as a major reason for wasteful energy consumption in computing systems. It is essential for programmers to audit the energy usage of their program code and apply code optimization to reduce energy consumption. While power and energy are already among the top issues that need to be solved, information leakage using shared resource in multi-core hardware has been becoming a fast growing concern. Over the past years, it has been shown many times that multicore hardware resources are vulnerable and can easily be exploited as covert timing channels to leak sensitive information at high speed. Unfortunately, there is no existing hardware-supported auditing for such types of information leakage.
As factors such as power, energy and information leakage are becoming more critical, software developers and system administrators are urgently looking for appropriate tools to address such challenges, just like they used to rely on performance counters for solving performance issues. The next generation hardware monitoring infrastructure should take users need into consideration, and provide sufficient and convenient resource auditing support beyond just performance. It will not only enable the programmers to improve the scalability of their software programs by better using power budget, and to reduce cost by improving the energy efficiency of their program code, but it will also help system administrators enhance the level of trust of their systems by tracking and removing information leakage sources.
In this dissertation, we proposed and explored the design of three novel resource auditing techniques as part of the next generation hardware monitoring infrastructure, namely, application power auditing, application energy auditing, and covert timing channel auditing. The design methodologies of the three techniques share the same goal of leveraging hardware support to enable the gathering of resource usage information in an efficient and cost-effective manner. The hardware support is also equipped with lightweight software support to maximize the flexibility of usages. Overall, the goal of this work is to push the hardware monitoring support to the next level, and enable the programmer to efficiently address a spectrum of existing and emerging system issues.",
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notes = "Chen_gwu_0075A_12567.pdf
Supervisor: Guru Prasadh Venkataramani",
