Optimization of Combinational Logic Circuits Using NAND Gates and Genetic Programming
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- @InCollection{Rajaei:2011:SCIA,
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author = "Arezoo Rajaei and Mahboobeh Houshmand and
Modjtaba Rouhani",
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title = "Optimization of Combinational Logic Circuits Using
NAND Gates and Genetic Programming",
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booktitle = "Soft Computing in Industrial Applications",
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publisher = "Springer",
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year = "2011",
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editor = "Antonio Gaspar-Cunha and Ricardo Takahashi and
Gerald Schaefer and Lino Costa",
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volume = "96",
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series = "Advances in Intelligent and Soft Computing",
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pages = "405--414",
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keywords = "genetic algorithms, genetic programming",
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isbn13 = "978-3-642-20504-0",
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DOI = "doi:10.1007/978-3-642-20505-7_36",
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abstract = "The design of an optimised logic circuit that
implements a desired Boolean function is of interest.
Optimisation can be performed in terms of different
objectives. They include optimising the number of
gates, the number of levels, the number of transistors
of the circuit, etc. In this paper, we describe an
approach using genetic programming to optimize a given
Boolean function concerning the above mentioned
objectives. Instead of commonly used set of gates, i.e.
{AND, OR, NOT, XOR}, we use the universal NAND gates
which lead to a faster and more compact circuit. The
traditional gate minimisation techniques produce
simplified expressions in the two standard forms: sum
of products (SOP) or product of sums (POS). The SOP
form can be transformed to a NAND expression by a
routine, but the transformation does not lead to
optimized circuit; neither in terms of the number of
gates, nor the number of levels. Experimental results
show our approach produces better results compared to
transforming the SOP form to the NAND expression, with
respect to the number of gates, levels and transistors
of the circuit.",
- }
Genetic Programming entries for
Arezoo Rajaei
Mahboobeh Houshmand
Modjtaba Rouhani
Citations