Transient error mitigation by means of approximate logic circuits

Created by W.Langdon from gp-bibliography.bib Revision:1.8081

@PhdThesis{Thesis_AJSC,

• author = "Antonio Jose {Sanchez Clemente}",
• title = "Transient error mitigation by means of approximate logic circuits",
• school = "Universidad Carlos III de Madrid",
• year = "2017",
• address = "Spain",
• keywords = "genetic algorithms, genetic programming, EHW",
• URL = "http://hdl.handle.net/10016/26338",
• URL = "https://e-archivo.uc3m.es/bitstream/handle/10016/26338/tesis_antonio-jose_sanchez_clemente_2017.pdf?sequence=1&isAllowed=y",
• URL = "https://aplicaciones.uc3m.es/webTesis/principal.do?estudio1=45&estudio2=35&estudio3=39&estudio4=116&anio=2017",
• size = "257 pages",
• abstract = "The technological advances in the manufacturing of electronic circuits have allowed to greatly improve their performance, but they have also increased the sensitivity of electronic devices to radiation-induced errors. Among them, the most common effects are the SEEs, i.e., electrical perturbations provoked by the strike of high-energy particles, which may modify the internal state of a memory element (SEU) or generate erroneous transient pulses (SET), among other effects. These events pose a threat for the reliability of electronic circuits, and therefore fault-tolerance techniques must be applied to deal with them.

  The most common fault-tolerance techniques are based in full replication (DWC or TMR). These techniques are able to cover a wide range of failure mechanisms present in electronic circuits. However, they suffer from high overheads in terms of area and power consumption. For this reason, lighter alternatives are often sought at the expense of slightly reducing reliability for the least critical circuit sections. In this context, a new paradigm of electronic design is emerging, known as approximate computing, which is based on improving circuit performance in exchange for slight modifications of the intended functionality. This is an interesting approach for the design of lightweight fault-tolerant solutions, which has not been studied in depth yet.

  The main goal of this thesis consists in developing new lightweight fault-tolerant techniques with partial replication by means of approximate logic circuits. These circuits can be designed with great flexibility. This way, the level of protection as well as the overheads can be adjusted at will depending on the necessities of each application. However, finding optimal approximate circuits for a given application is still a challenge.

  In this thesis a method for approximate circuit generation is proposed, denoted as fault approximation, which consists in assigning constant logic values to specific circuit lines. On the other hand, several criteria are developed to generate the most suitable approximate circuits for each application, by using this fault approximation mechanism. These criteria are based on the idea of approximating the least testable sections of circuits, which allows reducing overheads while minimising the loss of reliability. Therefore, in this thesis the selection of approximations is linked to testability measures.

  The first criterion for fault selection developed in this thesis uses static testability measures. The approximations are generated from the results of a fault simulation of the target circuit, and from a user-specified testability threshold. The amount of approximated faults depends on the chosen threshold, which allows to generate approximate circuits for different tradeoffs. Although this approach was initially intended for combinational circuits, an extension to sequential circuits has been performed as well, by considering the flip-flops as both inputs and outputs of the combinational part of the circuit. The experimental results show that this technique achieves a wide scalability and an acceptable tradeoff between reliability and overheads. In addition, its computational complexity is very low.

  However, the selection criterion based in static testability measures has some drawbacks. Adjusting the trade-off of the generated approximate circuits by means of the approximation threshold is not intuitive, and the static testability measures do not take into account the changes as long as faults are approximated. Therefore, an alternative criterion is proposed, which is based on dynamic testability measures. With this criterion, the testability of each fault is computed by means of an implication-based probability analysis. The probabilities are updated with each new approximated fault, in such a way that in each iteration the most beneficial approximation is chosen, that is, the fault with the lowest probability. In addition, the computed probabilities allow to estimate the level of protection against faults that the generated approximate circuits provide. Therefore, it is possible to generate circuits which stick to a target error rate. By modifying this target, circuits for different trade-offs can be obtained. The experimental results show that this new approach is able to stick to the target error rate with reasonably good precision. In addition, the approximate circuits generated with this technique show better characteristics than with the approach based in static testability measures. Finally, the fault implications have been reused too in order to implement a new type of logic transformation, which consists in substituting functionally similar nodes.

  Once the fault selection criteria have been developed, they are applied to different scenarios. First, an extension of the proposed techniques to FPGAs is performed, taking into account the specificities of this kind of circuits. This approach has been validated by means of radiation experiments, which show that a partial replication with approximate circuits can be even more robust than a full replication approach, because a smaller area reduces the probability of SEE occurrence. Besides, the proposed techniques have been applied to a real application circuit as well, in particular to the microprocessor ARM Cortex M0. A set of software benchmarks is used to generate the required testability measures. Finally, a comparative study of the proposed approaches with approximate circuit generation by means of evolutionary techniques have been performed. These approaches are able to generate multiple circuits by trial and error, thus reducing the possibility of falling into local minima. The experimental results demonstrate that the circuits generated with evolutionary approaches present slightly better trade-offs than the circuits generated with the techniques here proposed, although with a much higher computational effort.

  In summary, several original error mitigation techniques with approximate logic circuits are proposed. These approaches are demonstrated in various scenarios, showing that the scalability and adaptability to the requirements of each application are their main virtues.",

• notes = "supervisor Luis Entrena Arrontes",

}

Genetic Programming entries for Antonio Jose Sanchez-Clemente

Citations