- author = "Zdenek Vasicek and Lukas Sekanina",
- title = "A global postsynthesis optimization method for combinational circuits",
- booktitle = "Design, Automation Test in Europe Conference Exhibition (DATE), 2011",
- year = "2011",
- editor = "Lothar Thiele",
- pages = "1525--1528",
- address = "Grenoble, France",
- month = "14-18 " # mar,
- publisher = "IEEE",
- isbn13 = "978-1-61284-208-0",
- keywords = "genetic algorithms, genetic programming, cartesian genetic programming, Analog circuits, Benchmark testing, Circuit synthesis, Indexes, Logic gates, Runtime",
- ISSN = "1530-1591",
-
URL = "
http://www.fit.vutbr.cz/research/view_pub.php?id=9521",
-
URL = "http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=5763326",
-
DOI = "
doi:10.1109/DATE.2011.5763326",
- size = "4 pages",
- abstract = "A genetic programming-based circuit synthesis method is proposed that enables to globally optimise the number of gates in circuits that have already been synthesised using common methods such as ABC and SIS. The main contribution is a proposal for a new fitness function that enables to significantly reduce the fitness evaluation time in comparison to the state of the art. The fitness function performs optimised equivalence checking using a SAT solver. It is shown that the equivalence checking time can significantly be reduced when knowledge of the parent circuit and its mutated offspring is taken into account. For a cost of a random, results of conventional synthesis conducted using SIS and ABC were improved by 20--40percent for the LGSynth93 benchmarks.",
-
notes = "Silver winner 2011 HUMIES GECCO 2011
Faculty of Information Technology, Bmo University of Technology, Brno, Czech Republic
Also known as \cite{5763326}",
