Cartesian genetic algorithm for Boolean synthesis with power consumption restriction

Created by W.Langdon from gp-bibliography.bib Revision:1.8612

@InProceedings{Vitola:2014:CWCAS,

• author = "Jaime Vitola and Cesar Pedraza and Jose I. Martinez and Johanna Sepulveda",
• booktitle = "5th IEEE Colombian Workshop on Circuits and Systems (CWCAS 2014)",
• title = "Cartesian genetic algorithm for Boolean synthesis with power consumption restriction",
• year = "2014",
• address = "Bogota, Colombia",
• month = "16-17 " # oct,
• keywords = "genetic algorithms, genetic programming, cartesian genetic programming",
• DOI = "10.1109/CWCAS.2014.6994608",
• size = "4 pages",
• abstract = "The use of evolutionary algorithms in the Boolean synthesis is an interesting technique to generate hardware structures with multiple restrictions. However, one characteristic of these algorithms is their high computational load. This paper presents the implementation of a parallel cartesian genetic programming (CGP) for Boolean synthesis on a FPGA-CPU based platform. Power consumption and critical path restrictions were included into the algorithm in order to generate structures to solve any problem. As results a 2-bit comparator is presented, as well as response time and data transitions probability.",
• notes = "Also known as \cite{6994608}",

}

Genetic Programming entries for Jaime Vitola Cesar Pedraza Bonilla Jose Ignacio Martinez Torre Martha Johanna Sepulveda Florez

Citations