A SAT-based fitness function for evolutionary optimization of polymorphic circuits

Created by W.Langdon from gp-bibliography.bib Revision:1.8051

@InProceedings{Sekanina:2012:DATE2,

• author = "Lukas Sekanina and Zdenek Vasicek",
• title = "A SAT-based fitness function for evolutionary optimization of polymorphic circuits",
• booktitle = "Design, Automation Test in Europe Conference Exhibition (DATE), 2012",
• year = "2012",
• month = "12-16 " # mar,
• pages = "715--720",
• size = "6 pages",
• abstract = "Multifunctional (or polymorphic) gates have been used as building blocks for multifunctional circuits that are capable of performing various logic functions under different settings of control signals. In order to effectively synthesise polymorphic circuits, several methods have been developed in the recent years. Unfortunately, the methods are applicable for small circuits only. In this paper, we propose a SAT-based functional equivalence checking algorithm to eliminate the fitness evaluation time which is the most critical overhead for genetic programming-based design and optimisation of complex polymorphic circuits. The proposed approach has led to a 20percent-40percent reduction in gate count with respect to the solutions created using the polymorphic multiplexing.",
• keywords = "genetic algorithms, genetic programming, SAT-based fitness function, SAT-based functional equivalence checking algorithm, complex polymorphic circuit optimisation, evolutionary optimisation, genetic programming-based design, logic function, multifunctional circuit, multifunctional gate, polymorphic circuit synthesis, polymorphic gate, polymorphic multiplexing, circuit optimisation, computability, logic gates",
• URL = "http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6176563",
• DOI = "doi:10.1109/DATE.2012.6176563",
• ISSN = "1530-1591",
• notes = "Also known as \cite{6176563}",

}

Genetic Programming entries for Lukas Sekanina Zdenek Vasicek

Citations