Towards Self-Adaptive Caches: a Run-Time Reconfigurable Multi-Core Infrastructure
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- @InProceedings{ho-ka-pl-14a,
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author = "Nam Ho and Paul Kaufmann and Marco Platzner",
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title = "Towards Self-Adaptive Caches: a Run-Time
Reconfigurable Multi-Core Infrastructure",
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booktitle = "International Conference on Evolvable Systems, ICES
2014",
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year = "2014",
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pages = "31--37",
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month = "9-12 " # dec,
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publisher = "IEEE",
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keywords = "genetic algorithms, genetic programming, Cartesian
Genetic Programming, EHW",
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DOI = "doi:10.1109/ICES.2014.7008719",
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size = "7 page",
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abstract = "This paper presents the first steps towards the
implementation of an evolvable and self-adaptable
processor cache. The implemented system consists of a
run-time reconfigurable memory-to-cache address mapping
engine embedded into the split level one cache of a
Leon3 SPARC processor as well as of an measurement
infrastructure able to profile microarchitectural and
custom logic events based on the standard Linux
performance measurement interface perf_event. The
implementation shows, how reconfiguration of the very
basic processor properties, and fine granular profiling
of custom logic and integer unit events can be realised
and meaningfully used to create an adaptable multi-core
embedded system.",
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notes = "EvoCache Xilinx FPGA. Also known as \cite{7008719}",
- }
Genetic Programming entries for
Nam Ho
Paul Kaufmann
Marco Platzner
Citations