Parallel Optimization of Transistor Level Circuits Using Cartesian Genetic Programming
Created by W.Langdon from
gp-bibliography.bib Revision:1.8051
- @InProceedings{Mrazek:2017:GECCO,
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author = "Vojtech Mrazek and Zdenek Vasicek",
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title = "Parallel Optimization of Transistor Level Circuits
Using Cartesian Genetic Programming",
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booktitle = "Proceedings of the Genetic and Evolutionary
Computation Conference Companion",
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series = "GECCO '17",
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year = "2017",
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isbn13 = "978-1-4503-4939-0",
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address = "Berlin, Germany",
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pages = "1849--1856",
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size = "8 pages",
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URL = "http://doi.acm.org/10.1145/3067695.3084212",
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DOI = "doi:10.1145/3067695.3084212",
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acmid = "3084212",
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publisher = "ACM",
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publisher_address = "New York, NY, USA",
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keywords = "genetic algorithms, genetic programming, cartesian
genetic programming, digital circuits, evolutionary
optimization, parallel systems, transistor-level",
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month = "15-19 " # jul,
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abstract = "The aim of the paper is to introduce a new parallel
approach to evolutionary optimization of digital
circuits described on transistor level. The
evolutionary optimization is guided by the fitness
function employing a simulator of candidate circuits. A
new discrete simulator was introduced to achieve a good
trade-off between precision and cost of circuit
evaluations. The simulator is based on event-driven
simulation. Precise numeric SPICE simulator is
regularly called to validate simulation results. To
increase the speed of evolution, three parallel
approaches were proposed: (i) thread level parallelism,
(ii) multiple computing nodes which collectively
communicate and distribute the best solution, and (iii)
client-server architecture eliminating a limited count
of SPICE simulator instances.",
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notes = "Also known as \cite{Mrazek:2017:POT:3067695.3084212}
GECCO-2017 A Recombination of the 26th International
Conference on Genetic Algorithms (ICGA-2017) and the
22nd Annual Genetic Programming Conference (GP-2017)",
- }
Genetic Programming entries for
Vojtech Mrazek
Zdenek Vasicek
Citations