- author = "Zdenek Vasicek and Lukas Sekanina",
- title = "Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware",
- journal = "Genetic Programming and Evolvable Machines",
- year = "2011",
- volume = "12",
- number = "3",
- pages = "305--327",
- month = sep,
- note = "Special Issue Title: Evolvable Hardware Challenges",
- keywords = "genetic algorithms, genetic programming, Cartesian Genetic Programming",
- ISSN = "1389-2576",
-
DOI = "
doi:10.1007/s10710-011-9132-7",
- size = "23 pages",
- abstract = "We use a formal verification algorithm to reduce the fitness evaluation time for evolutionary post-synthesis optimisation in evolvable hardware. The proposed method assumes that a fully functional digital circuit is available. A post-synthesis optimisation is then conducted using Cartesian Genetic Programming (CGP) which uses a satisfiability problem solver to decide whether a candidate solution is functionally correct or not. It is demonstrated that the method can optimise digital circuits of tens of inputs and thousands of gates. Furthermore, the number of gates was reduced for the LGSynth93 benchmark circuits by 37.8percent on average with respect to results of the conventional SIS tool.",
-
notes = "Silver winner 2011 HUMIES GECCO 2011
",
- affiliation = "Faculty of Information Technology, Brno University of Technology, Brno, Czech Republic",
