Created by W.Langdon from gp-bibliography.bib Revision:1.7954
We present a fast, compact representation of the tree structures in FPGA logic which can be evolved as well as executed without external intervention. Execution of all tree nodes occurs in parallel and is pipelined. Furthermore, the compact layout enables multiple trees to execute concurrently, dramatically speeding up the fitness evaluation phase. An elegant technique for implementing the evolution phase, made possible by self-reconfiguration, is also presented.
We use two GP problems as benchmarks to compare the performance of logic mapped onto a Xilinx XC6264 FPGA against a software implementation running on a 200 MHz Pentium Pro PC with 64 MB RAM. Our results show a speedup of 19 for an arithmetic intensive problem and a speedup of three orders of magnitude for a logic operation intensive problem.",
FPL 1999",
Genetic Programming entries for Reetinder P S Sidhu Alessandro Mei Viktor K Prasanna