- author = "Reetinder P. S. Sidhu and Alessandro Mei and Viktor K. Prasanna",
- title = "Genetic Programming using Self-Reconfigurable {FPGAs}",
- booktitle = "9th International Workshop on Field Programmable Logic and Applications",
- editor = "Patrick Lysaght and James Irvine and Reiner Hartenstein",
- year = "1998",
- volume = "1673",
- series = "LNCS",
- pages = "301--312",
- address = "Glasgow, UK",
- publisher_address = "Berlin",
- month = "30 " # aug # " - 1 " # sep,
- publisher = "Springer-Verlag",
- publisher_address = "Berlin",
- keywords = "genetic algorithms, genetic programming, EHW",
- ISBN = "3-540-66457-2",
-
URL = "
http://ceng.usc.edu/~prasanna/papers/sidhuFPL99.ps",
-
URL = "
http://citeseer.ist.psu.edu/sidhu00selfreconfigurable.html",
-
DOI = "
doi:10.1007/b72332",
-
DOI = "doi:10.1007/978-3-540-48302-1_31",
-
abstract = "FPGA self-reconfiguration for efficient computation in
the context of Genetic Programming (GP). GP involves
evolving programs represented as trees and evaluating
their fitness, the latter operation consuming most of
the time.
We present a fast, compact representation of the tree structures in FPGA logic which can be evolved as well as executed without external intervention. Execution of all tree nodes occurs in parallel and is pipelined. Furthermore, the compact layout enables multiple trees to execute concurrently, dramatically speeding up the fitness evaluation phase. An elegant technique for implementing the evolution phase, made possible by self-reconfiguration, is also presented.
We use two GP problems as benchmarks to compare the performance of logic mapped onto a Xilinx XC6264 FPGA against a software implementation running on a 200 MHz Pentium Pro PC with 64 MB RAM. Our results show a speedup of 19 for an arithmetic intensive problem and a speedup of three orders of magnitude for a logic operation intensive problem.",
-
notes = "Department of EE-Systems, University of Southern
California, Los Angeles, USA
FPL 1999",
